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May 31st, 2014
10Gb/s Ethernet Platform Implementation
John Chaiyasarikul, Yumeng Xu, Shuguan Yang, Jian Zhong
01
APPLICATIONS
✤ DATA Centers ✤ Finance ✤ Clusters
10Gb/s Ethernet Platform Implementation John Chaiyasarikul, Yumeng - - PowerPoint PPT Presentation
10Gb/s Ethernet Platform Implementation John Chaiyasarikul, Yumeng - - PowerPoint PPT Presentation
10Gb/s Ethernet Platform Implementation John Chaiyasarikul, Yumeng Xu, Shuguan Yang, Jian Zhong May 31st, 2014 APPLICATIONS DATA Centers Finance Clusters 01 $1.6k $3.2k Dev Kit Unavailable $300 + Low Power Dev Kit
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Motivation/Significance
$1.6k – $3.2k $3.6k Dev Kit Unavailable $300 + Low Power
Dev Kit Unavailable
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Architecture of the Design
HSMC
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Interfaces
- I. HSMC - 4 lanes @ 3.125Gb/s
- II. XAUI/XGMII - 8 Bytes with 8bits control signals
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Interfaces
- III. Avalon ST - Unidirectional flow of data @ 156.25MHz.
- IV. Avalon MM -A standard address-based read/write
interface typical of master-slave connections.
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Pin Assignment Matching
Stratix IV Top Level Stratix IV Schematic HSMC PORT NUMBER SoCKit Top Level SoCKit Schematic
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Configuration
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MAC
λ Convert between XGMII and Avalon ST Interfaces λ Calculate Checksum λ Check or Append Checksum λ Fast/Transparent MAC λ 3 clock cycle latency rx λ 2 clock cycle latency tx SLIDE 10
MAC
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CRC-32
For parallel computing refer to www.cypress.com/?docID=31573 and easics.com
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Connections
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ST/MM
Problem: Data is received and transmitted with a bus width of 64 bits of data, MM interface supports
- nly 32 bits with no control signals
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