5/15/2019 Multipliers Outline multiplicand Digital CMOS Design b - - PowerPoint PPT Presentation

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Pirouz Bazargan Sabet February 2010 Digital Design

Outline

Arithmetic Operators Digital CMOS Design

Adders Comparators Shifters Multipliers Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Multipliers

Two natural numbers A A A A and B B B B coded on n bits the result of A A A A × B B B B is coded on 2n bits Classic method as learned in primary school

Pirouz Bazargan Sabet February 2010 Digital Design

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 s s s s0 s s s s1 1 1 1 s s s s2 2 2 2 s s s s3 3 3 3 s s s s4 4 4 4 s s s s5 5 5 5 s s s s6 6 6 6 s s s s7 7 7 7 s s s s8 8 8 8 s s s s9 9 9 9 s s s s10 10 10 10 s s s s11 11 11 11 s s s s12 12 12 12 s s s s13 13 13 13 s s s s14 14 14 14 s s s s15 15 15 15 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7

multiplicand

Multipliers

b b b b0 and

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7

Multipliers

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Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7 1 1 1 1 1 1

ck ck ck ck

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7 1 1 1 1 1 1

ck ck ck ck

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7 1 1 1 1 1

ck ck ck ck

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7 1 1 1 1 1

ck ck ck ck

Multipliers

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Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : sequential multiplier 2n bit adder

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7 1 1 1 1 1 1 1 1 1

ck ck ck ck

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier

a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 s s s s0 s s s s1 1 1 1 s s s s2 2 2 2 s s s s3 3 3 3 s s s s4 4 4 4 s s s s5 5 5 5 s s s s6 6 6 6 s s s s7 7 7 7 s s s s8 8 8 8 s s s s9 9 9 9 s s s s10 10 10 10 s s s s11 11 11 11 s s s s12 12 12 12 s s s s13 13 13 13 s s s s14 14 14 14 s s s s15 15 15 15 b b b b0 b b b b1 1 1 1 b b b b2 2 2 2 b b b b3 3 3 3 b b b b4 4 4 4 b b b b5 5 5 5 b b b b6 6 6 6 b b b b7 7 7 7

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier

At each level the operand of the adder is a partial product (conditioned by the corresponding b b b bi i i i) adder adder adder adder adder adder adder

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

2 3 1 0 1 0 1 1 1

= 78

Multipliers

half less terms → half less partial products

= × 2

• =

+ 2 × 2

⁄

• ∈ 0,1

= 2 × 2 + 3 × 2 + 0 × 2 + 1 × 2 = 78

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Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

Multipliers

= × 2

• =

+ 2 × 2

⁄

• = × 2 + × 2 +

× 2 + × 2 + × 2 + × 2 + × 2 + × 2 = + 2 × 2 + + 2 × 2 + + 2 × 2 + + 2 × 2

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

Multipliers

= × 2

• ∈ 0,1

∈ 0,1, 2, 3 = + 2 × 2

⁄

• 2 = 4 − 2 !!

= + 4 − 2 × 2

⁄

• Pirouz Bazargan Sabet

February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

Multipliers

= + 4 − 2 × 2

⁄

• = + 4 − 2 × 2 +

+ 4 − 2 × 2 + + 4 − 2 × 2 + + 4 − 2 × 2 = + 0 − 2 × 2 + + − 2 × 2 + + − 2 × 2 + + − 2 × 2 + × 2!

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

next weight

Multipliers

previous weight

= × 2

• ∈ 0,1

= + 4 − 2 × 2

⁄

• = + − 2 × 2

⁄

• = ′ × 2

⁄

• ′ ∈ −2, −1, 0, 1, 2

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Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

• 2

1 1

Booth encoding

0 1 0 1 1 1

= 78

Multipliers

= + − 2 × 2

⁄

• = −2 × 2 + 0 × 2 + 1 × 2 + 1 × 2 + 0 × 2! = 78

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier Improvement : Reduce the number of partial products

recoded multiplicand bit (b’ b’ b’ b’i i i i)

• 2

2 2 2 1 1 1 1 2 2 2 2

• 1

1 1 1 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 1 1 1 1 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 1 1 1 1 a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 multiplier a a a a0 a a a a1 1 1 1 a a a a2 2 2 2 a a a a3 3 3 3 a a a a4 4 4 4 a a a a5 5 5 5 a a a a6 6 6 6 a a a a7 7 7 7 partial product a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier

b’ b’ b’ b’0 b’ b’ b’ b’4 4 4 4

Improvement : Reduce the number of partial products An additional partial product is generated to take into account the input carry in case of subtraction if -1 or -2

b’ b’ b’ b’6 6 6 6 b’ b’ b’ b’2 2 2 2

if -1 or -2

c c c c0 c c c c2 2 2 2 c c c c4 4 4 4 c c c c6 6 6 6 1 1 1 1

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : parallel multiplier

s s s s0 s s s s1 1 1 1 s s s s2 2 2 2 s s s s3 3 3 3 s s s s4 4 4 4 s s s s5 5 5 5 s s s s6 6 6 6 s s s s7 7 7 7 s s s s8 8 8 8 s s s s9 9 9 9 s s s s10 10 10 10 s s s s11 11 11 11 s s s s12 12 12 12 s s s s13 13 13 13 s s s s14 14 14 14 s s s s15 15 15 15 b’ b’ b’ b’0 a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8 b’ b’ b’ b’2 2 2 2 b’ b’ b’ b’4 4 4 4 b’ b’ b’ b’6 6 6 6 b’ b’ b’ b’8 8 8 8 a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8 a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8 a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8 a’ a’ a’ a’0 a’ a’ a’ a’1 1 1 1 a’ a’ a’ a’2 2 2 2 a’ a’ a’ a’3 3 3 3 a’ a’ a’ a’4 4 4 4 a’ a’ a’ a’5 5 5 5 a’ a’ a’ a’6 6 6 6 a’ a’ a’ a’7 7 7 7 a’ a’ a’ a’8 8 8 8 c c c c0 c c c c1 1 1 1 c c c c2 2 2 2 c c c c3 3 3 3 c c c c4 4 4 4 c c c c5 5 5 5 c c c c6 6 6 6 c c c c7 7 7 7

Multipliers

c c c c0 c c c c1 1 1 1 c c c c2 2 2 2 c c c c3 3 3 3 c c c c4 4 4 4 c c c c5 5 5 5 c c c c6 6 6 6 c c c c7 7 7 7

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Pirouz Bazargan Sabet February 2010 Digital Design

adder adder adder adder adder adder adder

Implementation : parallel multiplier

adder adder adder adder adder Each partial product is conditioned by the corresponding Booth encoded multiplicand bit b’ b’ b’ b’i i i i

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : fast parallel multiplier Basically for a n×n multiplication, we have to add n partial products (2n-bit numbers)

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Adding two natural numbers Adding three natural numbers adder a a a a b b b b adder c c c c delay

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

c c c ci+1 i+1 i+1 i+1 b b b bi i i i c c c ci i i i

Adding three natural numbers s s s si

i i i =

= = = a a a ai

i i i⊕

⊕ ⊕ ⊕ b b b bi

i i i ⊕

⊕ ⊕ ⊕ c c c ci

i i i

c c c ci+1

i+1 i+1 i+1 =

= = = a a a ai

i i i.b

.b .b .bi

i i i +

+ + + a a a ai

i i i.c

.c .c .ci

i i i +

+ + + b b b bi

i i i.c

.c .c .ci

i i i

the expressions are symmetrical in regard of a, b a, b a, b a, b and c c c c

a a a ai i i i s s s si i i i

A full adder creates 2 numbers from 3

b b b bi i i i c c c ci i i i t t t ti+1 i+1 i+1 i+1

FA

Multipliers

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Pirouz Bazargan Sabet February 2010 Digital Design

Adding three natural numbers

t t t t1 1 1 1 b b b b0 0 c c c c0 a a a a0 s s s s0

FA

t t t t2 2 2 2 b b b b1 1 1 1 c c c c1 1 1 1 a a a a1 1 1 1 s s s s1 1 1 1

FA

t t t t3 3 3 3 b b b b2 2 2 2 c c c c2 2 2 2 a a a a2 2 2 2 s s s s2 2 2 2

FA

t t t t4 4 4 4 b b b b3 3 3 3 c c c c3 3 3 3 a a a a3 3 3 3 s s s s3 3 3 3

FA

t t t t5 5 5 5 b b b b4 4 4 4 c c c c4 4 4 4 a a a a4 4 4 4 s s s s4 4 4 4

FA Carry Save Adder (CSA) adder

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : fast parallel multiplier Basically for a n×n multiplication, we have to add n partial products (2n-bit numbers) Use CSA (Carry Save Adder) to reduce 3 partial products into 2

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : fast parallel multiplier

CSA CSA CSA CSA

8 partial products # of CSA layers ≈ log3/2 (n/2)

CSA CSA Adder

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : fast parallel multiplier # of CSA layers ≈ 2 log (n/2) 32×32 bits multiplier 32 22 15 2 10 7 5 4 3 32×32 bits multiplier 32 16 8 4 2 Using 4 2 reduction leads to a more regular hardware implementation

CSA CSA

Multipliers

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Pirouz Bazargan Sabet February 2010 Digital Design

Implementation : fast parallel multiplier 32×32 bits multiplier 32 22 15 2 10 7 5 4 3 2 3 4 6 9 42 13 19 28 The margin on the number of ‘partial products’ can be used to extended the functionality of the multiplier

Multipliers

Pirouz Bazargan Sabet February 2010 Digital Design

Two natural numbers A and B coded on n bits How it works if B < B < B < B < 0 0 ?

Multipliers

& = ' × relative & = ' × = −' × − = '̅ + 1 × ) + 1 & = '̅ × ) + '̅ + ) + 1

Pirouz Bazargan Sabet February 2010 Digital Design

Multiply and add

Multipliers

& = ' × + * if B < B < B < B < 0 0 ? & = ' × + * = −' × − + * & = '̅ + 1 × ) + 1 + C & = '̅ × ) + '̅ + ) + * + 1

Pirouz Bazargan Sabet February 2010 Digital Design

Multiply and subtract

Multipliers

if B > 0 B > 0 B > 0 B > 0 ? & = * − ' × & = * + ' × − & = * + ' × − = * + ' × ) + '