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A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier James Lin, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan b. Matsuzawa & Okada Lab y Outline

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SLIDE 1

James Lin, Zule Xu, Masaya Miyahara, and Akira Matsuzawa Tokyo Institute of Technology, Japan

A 0.5-to-1 V 9-bit 15-to-90 MS/s Digitally Interpolated Pipelined-SAR ADC Using Dynamic Amplifier

Matsuzawa & Okada Lab

b.

y

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SLIDE 2

2

Outline

  • Motivation
  • Digital Interpolation
  • Circuit Design
  • Measurement Results
  • Conclusion
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SLIDE 3

3

Conventional Pipelined-SAR ADC

  • Pipelined-SAR ADCs are sensitive to inter-stage

gain variation similar to pipelined ADCs

[1] J. Zhong, et al., A-SSCC 2012. [2] B. Verbruggen, et al., VLSI Circuits 2013. [3] F. van der Goes, et al., ISSCC 2014.

Digital Error Corr. SAR1 Vin Dout A SAR2a n m Vres D2 D1 Calibration [1]-[3]

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SLIDE 4

Analog Interpolation

  • For pipelined ADCs, interpolation can be used

to alleviate absolute gain requirement [4]

4

[4] J. Lin, et al., CICC 2013. A1a A1b

Vref to A2a to A2b Via Vib Dynamic Amp. 01 11 01 Vrefn Vrefp Vin Any Gain Embedded references

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SLIDE 5

5

Outline

  • Motivation
  • Digital Interpolation
  • Circuit Design
  • Measurement Results
  • Conclusion
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SLIDE 6

Digitally Interpolated Pipelined-SAR

  • Digital interpolation is proposed for its

simplicity and robustness

6 Digital Interpolator SAR1 Vin Dout A SAR2a SAR2b n m m Vres Va/b D2a D2b D1 A×Vb A×Va

±½LSB t Vin t Vres t A×Va/b t Va/b VLSB1

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SLIDE 7

Insensitive to Inter-Stage Gain

  • Outputs of the second stage is a fractional

representation of the original residue

7 A SAR2a SAR2b Vres Va or Vb D2a D2b A×Vb A×Va

±½LSB

A×Va A×Vb A×Va/b t A×Vres

A×VLSB1

D2a+D2b = 2A×Vres D2a-D2b = A×VLSB1 D2a = D{A×(Vres+½VLSB1)} D2b = D{A×(Vres-½VLSB1)} = Vres VLSB1 (D2a+D2b)/2 D2a-D2b Dout = (D1+ )×2m- (D2a+D2b)/2 D2a-D2b

a

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SLIDE 8

Dynamic Amplifier

  • High speed at low supply voltage and

clock-scalable power consumption [5]

8

[5] J. Lin, et al., ISCAS 2011.

Pd = fCVDD

2

Pre-charge Phase Amplification Phase

Time Voltage

Voutp Voutn CLK Voc Vout Vout CMD: Common-mode voltage detector CLK Vinp Vinn

CMD

Voutp Voutn CLK

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SLIDE 9

Inter-Stage Gain Variation

  • Dynamic amplifier’s gain varies with supply voltage

 digital interpolation suppresses the ENOB degradation

9

5 10 15 20 25 30 7.0 7.5 8.0 8.5 9.0 ENOB (bit) dG/G (%)

Conventional Proposed

DG/G (%) ENOB (bit)

0.5 0.6 0.7 0.8 0.9 1.0 10 20 30 40 50 dG/G (%) Supply voltage (V)

Supply voltage (V) DG/G (%)

DG/G vs. Supply ENOB vs. DG/G

Gamp = a(VDD-Voc)/Veff , 1<a<2

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SLIDE 10

Up/Down Shift Error

  • Interpolation requires an accurate shift

instead of the conventional accurate gain

10

5 10 15 20 25 30 7.0 7.5 8.0 8.5 9.0

ENOB (bit) dVs/Vs (%)

Calculated Simulated

DVLSB1/VLSB1 (%) ENOB (bit)

DC/C ≈ 0.45%(3s)

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SLIDE 11

11

Outline

  • Motivation
  • Digital Interpolation
  • Circuit Design
  • Measurement Results
  • Conclusion
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SLIDE 12

Circuit Design Overview

  • ADC architecture
  • Self-clocking scheme
  • Shared dynamic amplifier
  • Ultra-low-voltage SAR ADCs

12

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SLIDE 13

ADC Architecture

  • Proposed ADC consists of two stages

 6b SAR ADC, 2×sampling CDACs, logic  Dynamic amplifier, 2×6b SAR ADCs, logic 13

Sampling CDAC1 Digital Interpolator On-Chip Sampling CDAC2

Timing Logic SAR1 (6b)

SWs<1:0>

SWs<0> SWs<1> SWh<0> SWh<1> SAR2b (6b)

SWh<1:0>

Vin Dout Amp Logic

CLKamp

CLK

CLKsar<1:0>

SAR2a (6b) Va/b A×Va A×Vb

  • D. Amp

(A)

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SLIDE 14

Self-Clocking

  • Simulated timing diagram to show the key steps

14

SAR1 CDAC1 SAR2b CDAC2 AMPSAR2a AMPSAR2b SAR2a

Sample (SAR1)

1 2 4 5 7 3 6 Start SAR1 Amplify upshifted Vres,CDAC2 for SAR2a Start SAR2a Start SAR2b Downshift Code transfer and upshift Reset Amplify downshifted Vres,CDAC2 for SAR2b

Time

Sample (CDAC1) Sample (SAR2a) Conv. Sample (SAR2b) Conv.

+½ LSB +½ LSB

  • ½ LSB
  • ½ LSB
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SLIDE 15

Shared Dynamic Amplifier

  • Same pair of amplifying transistors are shared

between the two second-stage SAR ADCs 15

Vinp Vinn SAR2a CMD SAR2b CMD CMD

Van Vap Vbn Vbp

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SLIDE 16

Ultra-Low-Voltage SAR ADCs

  • Virtual Vcm realized using capacitive

interpolation achieves high speed

16

Vrefp Vrefn

Cu/2

Van

Cu/2 16×Cu/2 16×Cu/2

Vap

2×Cu/2 2×Cu/2 Cu/2 Cu/2

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SLIDE 17

17

Outline

  • Motivation
  • Digital Interpolation
  • Circuit Design
  • Measurement Results
  • Conclusion
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SLIDE 18

Measured DNL and INL (0.6 V)

  • DNL:

+0.81/-0.40 LSB

  • INL:

+0.69/-0.85 LSB

18

128 256 384 512

  • 1.5
  • 1.0
  • 0.5

0.0 0.5 1.0 1.5 DNL (LSB) Digital code

DNL (LSB) Digital code

128 256 384 512

  • 1.5
  • 1.0
  • 0.5

0.0 0.5 1.0 1.5 INL (LSB) Digital code

Digital code INL (LSB)

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SLIDE 19

Measured SNDR and SFDR (0.6 V)

  • >49 dB of SNDR is measured up to 30 MS/s with an

ERBW >15 MHz

  • Consumes 481.6 mW (23% analog, 65% digital, 12%

reference) at 30 MS/s  FoM=68 fJ/conversion-step 19

SNDR & SFDR vs. fs SNDR & SFDR vs. fin

5 10 15 20 25 30 35 30 35 40 45 50 55 60 65 70 SFDR and SNDR (dB) Conversion rate (MS/s)

fin = 1 MHz SFDR SNDR

Conversion rate (MS/s) SNDR and SFDR (dB)

0.0 2.5 5.0 7.5 10.0 12.5 15.0 30 35 40 45 50 55 60 65 70 SFDR and SNDR (dB) Input frequency (MHz)

fs = 30 MS/s SFDR SNDR

Input frequency (MHz) SNDR and SFDR (dB)

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SLIDE 20

Measured SNDR and SFDR (0.6-1.0 V)

  • 0.6 V  30 MS/s, 68 fJ/conversion-step
  • 0.8 V  70 MS/s, 148 fJ/conversion-step
  • 1.0 V  90 MS/s, 247 fJ/conversion-step

20

20 40 60 80 100 120 140 30 40 50 60 70

SNDR @ 0.6 V SNDR @ 0.8 V SNDR @ 1.0 V

SFDR (dB) Conversion rate (MS/s)

fin = 1 MHz SFDR @ 0.6 V SFDR @ 0.8 V SFDR @ 1.0 V

Conversion rate (MS/s) SNDR and SFDR (dB)

10 20 30 40 50 30 40 50 60 70

SNDR @ 0.6 V SNDR @ 0.8 V SNDR @ 1.0 V

SFDR (dB) Input frequency (MHz)

SFDR @ 0.6 V SFDR @ 0.8 V SFDR @ 1.0 V

Input frequency (MHz) SNDR and SFDR (dB)

VDD = 0.6 V VDD = 0.8 V VDD = 1.0 V VDD = 0.6 V fs = 30 MS/s VDD = 0.8 V fs = 70 MS/s VDD = 1.0 V fs = 90 MS/s

SNDR & SFDR vs. fs SNDR & SFDR vs. fin

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SLIDE 21

Voltage-Scalable Conversion Rate

  • Conversion rate scales with the

supply voltage

21

0.5 0.6 0.7 0.8 0.9 1.0 20 40 60 80 100

  • Max. rate (MS/s)

Supply voltage (V)

Supply voltage (V) Conversion rate (MS/s)

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SLIDE 22

Third-Order Harmonic Distortion

  • ENOB degradation of the prototype ADC is due to

noise and a spur caused by interleaved CDACs

  • 3rd-order harmonic spur is <-65 dB

22

2 4 6 8 1 0 1 2 1 4 1 6

  • 1 2 0
  • 1 0 0
  • 8 0
  • 6 0
  • 4 0
  • 2 0

2 4 6 8 1 0 1 2 1 4 1 6

  • 1 2 0
  • 1 0 0
  • 8 0
  • 6 0
  • 4 0
  • 2 0
  • 20
  • 40
  • 60
  • 80
  • 100
  • 120
  • 20
  • 40
  • 60
  • 80
  • 100
  • 120

5 10 15 MHz 5 10 15 MHz

Normalized power (dB)

2 3 2 3

69.12 dB 65.97 dB

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SLIDE 23

Inter-Stage Gain Variation

  • Prototype ADC can operation in two modes:

Digital interpolation (proposed) External gain adjustment (conventional) 23

0.6 0.7 0.8 0.9 1.0 46 48 50 52 54 56

SNR (dB) Supply voltage (V)

fs = 30 MS/s, fin = 1 MHz Proposed Conventional

Supply voltage (V) SNR (dB) >4 dB

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SLIDE 24

Clock-Scalable Power Consumption

  • Dynamic nature of the entire ADC

 Power scales with the clock

24

20 40 60 80 100 120 140 0.0 1.0 2.0 3.0 4.0 5.0

Power consumption (mW) Sampling frequency (MS/s)

VDD=0.6 V VDD=0.8 V VDD=1.0 V

Conversion rate (MS/s) Power (mW)

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SLIDE 25

Chip Photo

  • Prototype ADC is fabricated in 65 nm CMOS with

the low threshold and deep N-well options

  • The occupied area is <0.11 mm2

25

350 mm 300 mm

Sampling CDAC1 Sampling CDAC2

SAR1

Amp

SAR2a SAR2b

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SLIDE 26

Performance Comparison

  • Digital interpolation and dynamic amplifier

realize a flexible ADC

26

[6] J. Shen, et al., JSSC 2008. [7] Y. J. Kim, et al., CICC 2007. [8] S. Lee, et al., JSSC 2012.

[6] [7] [8] This work Architecture Pipe Pipe Pipe Pipelined-SAR Resolution (bit) 8 10 12 9 Supply voltage (V) 0.5 0.5 0.8 0.5 0.6 0.8 1.0 0.5 0.6 0.8 1.0

  • Conv. rate (MS/s)

10 10 60 5 10 30 50 15 30 70 90 Power (mW) 2.4 3.0 19.2 0.24 0.56 1.61 4.07 0.20 0.48 1.92 3.14 ENOB (bit) 7.7 8.5 8.2 10.7 10.8 10.8 11.0 7.63 7.88 7.54 7.14 FoM (fJ/c.-s.) 1150 825 1118 28.0 30.9 31.1 41 67 68 148 247 Technology (nm) 90 130 65 65 Active area (mm2) 1.44 0.98 0.36 0.11

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SLIDE 27

27

Outline

  • Motivation
  • Digital Interpolation
  • Circuit Design
  • Measurement Results
  • Conclusion
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SLIDE 28

Conclusion

  • Digital interpolation is validated through a

0.5-to-1 V, 9b, 15-to-90 MS/s pipelined-SAR ADC

  • Proposed digitally interpolated pipelined-

SAR ADC achieves  Robustness to gain variation  Voltage-scalable  Clock-scalable

28

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SLIDE 29

Acknowledgement

29

This work was partially supported by NEDO, Huawei, Berkeley Design Automation for the use

  • f the Analog FastSPICE (AFS) Platform, and

VDEC in collaboration with Cadence Design Systems, Inc.

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SLIDE 30

30

Thank you for your interest!

James Lin, james@ssc.pe.titech.ac.jp