A 90nm Low-Power GSM/EDGE Multimedia- Enhanced Baseband Processor - - PowerPoint PPT Presentation

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A 90nm Low-Power GSM/EDGE Multimedia- Enhanced Baseband Processor - - PowerPoint PPT Presentation

Nov 15, 2023 560 likes •872 views

A 90nm Low-Power GSM/EDGE Multimedia- Enhanced Baseband Processor with 380MHz ARM9 and Mixed-Signal Extensions Steffen Buch 1) , Thomas Lftner 1) , Jrg Berthold 1) , Christian Pacha 1) , Georg Georgakos 1) , Guillaume Sauzon 1) , Olaf Hmke

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A 90nm Low-Power GSM/EDGE Multimedia- Enhanced Baseband Processor with 380MHz ARM9 and Mixed-Signal Extensions

Steffen Buch1), Thomas Lüftner1), Jörg Berthold1), Christian Pacha1), Georg Georgakos1), Guillaume Sauzon1), Olaf Hömke1), Jurij Beshenar 3), Peter Mahrla 1), Knut Just1), Peter Hober1), Stephan Henzler1,5), Doris Schmitt-Landsiedel5), Andre Yakovleff2), Axel Klein1), Richard Knight 4), Pramod Acharya1), Hamid Mabrouki2), Goulhamid Juhoor2), Matthias Sauer1)

1) Infineon Technologies, Munich, Germany 2) Infineon Technologies, Sophia Antipolis, France 3) Infineon Technologies, Xian, China 4) Infineon Technologies, Bristol, United Kingdom 5) Technical University of Munich, Germany

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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Target Application: Mid-Range Feature Phones

S-GOLD 3

MPxl Camera FM Radio

Bluetooth Engine A-GPS Engine

WLAN Engine

IrDA Transceiver Sensors

2G RF Transceiver

1 2 3 4 5 6 7 8 9 * #

Signaling LEDs Backlight Vibrator System Connector Battery

Power Management IC

Sec. Display

Main Display

U-GOLD (S-GOLD 3 + SPINNER1.1/1.1CR)

MMC

SIM Card SIM Card

F E M

3G RF Transceiver Application Enhanced Baseband Processor 3G L1 Co-Processor stacked

SDRAM Flash

! Baseband processor is

core component of platform

! Main use cases:

– Phone in standby – Voice call – Music replay – Video record/replay – Video telephony – Data transfer – Gaming

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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BB Processor Overview

6.6mm

! CMOS technology

– 90nm mixed-signal low-power – Dual gate-oxide for core devices – Triple well concept

! ARM926 for protocol stack

and applications

! TEAKlite DSP subsystem for

GSM/EDGE Layer 1

! Mixed signal subsystem

– High quality audio front-end – I/Q RF interface

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Core Performance Measurements

100 200 300 400 500 0.80 1.00 1.20 1.40 1.60

Supply Voltage VDD (V)

  • Max. Clock Frequency f (MHz)

AHB ARM ARM/Bus/ Mem.Cntrl. DSP

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ARM Performance for Intended Process Splits

Supply Voltage VDD (V)

1.0 1.1 1.2 1.3 1.4 1.5

Maximum Frequency f (MHz)

100 200 300 400 500

Nominal Process Slow Process Fast Process

Headroom for additional applications under worst case process conditions 254MHz 320MHz

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Performance Requirements

104 52 E-GPRS Data download 78 104 UMTS CS, MPEG-4 (15 fps, QCIF) Video telephony 52 254 MPEG-4 encode (20 fps, QVGA) Camcorder 26 26 MP3 Music replay 26 26 sleep mode paging GSM idle f (MHz) f (MHz) 52

DSP ARM Settings Application

6.60-AMR 26 GSM Voice call

! ARM (380MHz) and DSP

(300MHz) provide enough processing performance to fulfill requirements

! Still headroom for

– use case combinations and – currently unknown use cases

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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Circuit Level Power Saving Measures

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Implementation of Sleep-Transistor Concept

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Retention Flip Flop

! Motivation: Store data locally

for fast processor restart

! Idea: isolate retention cell

from flip flop input stage

! This work:

– Sense-amplifier based flip flop – Retention cell implemented in low leakage devices to eliminate gate leakage current – Isolation of the retention cell by transmission gates – Negligible delay increase due to fast switching transistors implemented in Reg-VT devices

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Retention Flip Flop: Operation

FF Performance: CLK-Q delay: tCLK-Q=150ps @ 10ps setup time,VDD=1.2V, T=110°C, slow process

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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System Level Power Optimization

! Scaling of clock frequency (f): clocks of main building

blocks are adjusted to the use case

" Reduction of dynamic power dissipation

! Scaling of core voltage (VDD CORE): core supply voltage

is adjusted to the use case

" Reduction of both dynamic and static power dissipation Power dissipation = α*f*C*VDD² + Ileak(VDD)*VDD

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‘GSM Sleep’ Configuration

Interrupt

  • Ctrl. Unit

Shared RAM System Ctrl., Power Mgmt. Clock Gen. DMA Ctrl.

Controller Subsystem DSP Subsystem

Application and I/O Interfaces: Display, MMC D-Cache I-Cache I-TCM D-TCM ARM926EJ DSP Peripherals: Interrupts, Timer, GSM Cipher, Equalizer, Channel Decoder, BB Receive 8PSK/GMSK Mod. GSM Syst. Peripherals TEAKLite DSP Core Bridge Bridge Bridge Bridge VDD PLL

Stand-By Domain

Multimedia & I/O Interfaces: Camera, Crypto Box, Fast IrDA VDD CORE VDD ANALOG VDD RTC VDD I/O 1 Power Supplies VDD I/O 2

1.05V 32kHz OFF OFF OFF OFF

RAM Boot ROM

  • Prog. Memory

Data Memory OFF IR Memory for EDGE Analog Macro: Audio FE, RF Interface

OFF OFF OFF 0 MHz 0 MHz OFF 0V

Multi Layer Advanced High Speed Bus (AHB)

1.35V 0V

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‘GSM Paging’ Configuration

Interrupt

  • Ctrl. Unit

Shared RAM System Ctrl., Power Mgmt. Clock Gen. DMA Ctrl.

Controller Subsystem DSP Subsystem

Application and I/O Interfaces: Display, MMC D-Cache I-Cache I-TCM D-TCM ARM926EJ DSP Peripherals: Interrupts, Timer, GSM Cipher, Equalizer, Channel Decoder, BB Receive 8PSK/GMSK Mod. GSM Syst. Peripherals TEAKLite DSP Core Bridge Bridge Bridge Bridge VDD PLL

Stand-By Domain

Multimedia & I/O Interfaces: Camera, Crypto Box, Fast IrDA VDD CORE VDD ANALOG VDD RTC VDD I/O 1 Power Supplies VDD I/O 2

1.05V 26MHz OFF OFF ON ON

RAM Boot ROM

  • Prog. Memory

Data Memory OFF IR Memory for EDGE Analog Macro: Audio FE, RF Interface

PARTLY ON PARTLY ON OFF 26 MHz ON

Multi Layer Advanced High Speed Bus (AHB)

26 MHz 2.5V 1.35V 0V

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‘GSM Voice Call’ Configuration

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‘E-GPRS Data Download’ Configuration

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‘Camcorder’ Configuration

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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20 40 60 80 100 120 140 0.9 1 1.1 1.2 1.3 1.4 1.5

Supply Voltage VDD (V) Power Dissipation P (mW)

26MHz 130MHz 254MHz

Measured ARM9 Power Dissipation

  • 49% reduction by

frequency scaling from 254MHz to 130MHz

  • 38% reduction by

voltage scaling from 1.35V to 1.05V Example:

High Performance Medium Performance Low Performance

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Measured Power Versus Applications

Power dissipation of Core and PLL voltage domains 20 40 60 80 100 120 140 160 180 200 G S M S l e e p M

  • d

e G S M P a g i n g G S M V

  • i

c e C a l l M P 3 M u s i c R e p l a y E

  • G

P R S D a t a D

  • w

n l

  • a

d V i d e

  • T

e l e p h

  • n

y C a m c

  • r

d e r [mW]

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Outline

! Introduction to target application ! BB chip overview and performance ! Circuit level power optimization ! System level power optimization ! Power measurement results ! Conclusion

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Conclusion

Presented GSM/EDGE BB Chip in 90nm demonstrates

! High performance ARM9: 380MHz @ 1.35V

– Enabling next generation mobile phone applications

! Use case driven implementation of power saving

features in a novel combination

– Standby domains and SRAMs in low leakage devices – Sleep transistors to switch off mixed-VT domains – Retention flip-flops – Frequency scaling – Voltage scaling

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Backups

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90nm CMOS Core Devices at VDD=1.2V

6 Level Metallization, 4 Thin Metal Levels, Triple Well on Non-Epi Substrate 5 300 Off-Current (pA/µm) 350/155 680/290 On-Current (µA/µm) 2.2 1.6 Oxide Thickness tox (nm) 550/513 370/290 Vt,sat (mV) 90 70 Poly Gate Length (nm) Low Leakage Device nFET/pFET Regular-Vt Device nFET/pFET

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References

Baseband and Wireless IC’s:

[1]

  • Y. Neuvo, “Cellular Phones as Embedded Systems”, ISSCC Dig. of Techn. Papers , Feb. 2004.

[2]

  • J. Kissing et al., ”A Fully Integrated SoC for GSM/GPRS in 130nm CMOS”, ISSCC Dig. of Techn. Papers , Feb. 2006.

[3]

  • P. Royannez et al., “90nm Low Leakage SoC Design Techniques for Wireless Applications”, ISSCC Digest of Technical Papers , Feb. 2005.

[4]

  • T. Kamei et al, “A Resume-Standby Application Processor for 3G Cellular Phones”, ISSCC Digest of Technical Papers,, Feb. 2004.

[5]

  • A. Coller et al.,, Reprogr. EDGE Baseband and Multimedia Handset SoC with 64Mb embedded DRAM”, ISSCC Dig. of Tech. Papers, Feb. 2005.

Low Power Circuit Techniques and CMOS Technology:

[6]

  • T. Schafbauer et al., “Integration of High-performance, Low-leakage and Mixed Signal Features into a 100nm CMOS Technology”, Symp. on VLSI

Technology, 2002. [7] S.V. Kosonocky et al., “Low-power circuits and technology for wireless digital systems”, IBM J. Research and Development, Vol. 47, No. 23, March 2003, pp. 283-298. [8] J.T. Kao et al., “Dual-Threshold Voltage Techniques for Low-Power Digital Circuits, , IEEE J. of Solid-State Circuits, Vol. 35, No. 7, July 2000, pp. 1009- 1018. [9] K.J. Nowka et al., “A 32-Bit Power PC System-on-a Chip With Support for Dynamic Voltage Scaling and Dynamic Frequency Scaling”, IEEE J. of Solid- State Circuits, Vol. 37, No. 11, Nov. 2002, pp. 1441-1447. [10] L.T. Clark, F. Rici, and M. Biyani, “Low Standby Power State Storage for Sub-130-nm Technologies, IEEE J. of Solid-State Circ., Vol. 40, No. 2, Febr. 2005, pp. 498-506. [11] S. Henzler et al, “Sleep Transistor Circuits for Fine-Grained Power Switch-Off with Short Power-Down Times”, ISSCC Dig. of Techn. Papers, Feb. 2005. [12] K. von Arnim et al., „A Low-Leakage 2.5GHz Skewed CMOS 32b Adder for Nanometer CMOS Technologies”, ISSCC Dig. of Techn. Papers, Feb. 2005. [13] M. Miyazaki et al., “A 1.2GIPS/W Microprocessor Using Speed-Adaptive Threshold-Voltage CMOS With Forward Bias, IEEE J. of Solid-State Circuits,

  • Vol. 37, No. 2, Febr. 2002, pp. 201-217., 2005.

[14] K. von Arnim et al, “Efficiency of Body Biasing in 90nm CMOS for Low Power Digital Circuits”, IEEE J. of Soli-State Circuits, Vol. 40, Mo.7, July 2005,

  • pp. 1549-1553.

[15] B. Nikolic, V. Oklobdzija, “Sense Amplifier-Based Flip Flop”, ISSCC Digest of Technical Papers, pp. 282-283, Feb. 1999.