A time to digital converter implemented on a ROACH2 board Genady - - PowerPoint PPT Presentation

A time to digital converter implemented on a ROACH2 board

Arizona State University 1) School of Earth and Space Exploration 2) School of Electrical, Computer and Energy Engineering 3) Department of Physics

Genady Pilyavsky (1,2) Adrian Sinclair (1) Philip Mauskopf (1,3)

Ongoing projects

Intensity interferometry

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• Modern take on Hanbury Brown and Twiss

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• Single photon detection

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• km++ baseline

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• Sub micro-arcsecond resolution

Ongoing projects

Ongoing projects

Image Inversion Interferometer

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• Modified Mach Zehnder Interferometer

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• Exoplanet Imaging

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• Contrast reduction

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• Sub-Rayleigh Resolution

Ongoing projects

• Gravitational Wave Measurement

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• Piggyback on other projects (Free space optical com)

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• See Sam Gordon
• Quantum Key Distribution

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• Modified Mach Zehnder Interferometer, again

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• One time pad generator
• SNSPD Readout

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• Multi-dimensional nanowire array

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• One dimensional “parallel”

Time to digital converter

• What does it do?

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• Accurate stop watch

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• Less data vs ADC *
• What do we want?

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• Continuous data stream

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• Multiple channels

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• High timing precision (~100 ps)

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• Minimal cross talk

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• Raw output

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• Cheap

Commercial test

• HydraHarp 400

○ Good timing (1ps) ○ Continuous ○ Black-boxed ○ Expensive ○ Low # of Ch.

• YVX-657

○ Good timing (32ps) ○ Cheap ○ Not continuous ○ Duty cycle ○ Crosstalk

• TTM8000

○ 82 ps ○ Cheap ○ Continuous ○ Crosstalk ○ Low # of Ch.

Commercial test: Cross talk

• TTM8000

○ Cheap, 82 ps, continuous ○ Crosstalk

Delay line approach : Overview

• Asynchronous input (GPIO)
• Based on the work by Harald Homulle

○ Series of CARRY4 Primitives

• Bubble filter
• 512 → 9 bit converter
• Dual-ported RAM
• Gigabit Ethernet output

Delay line approach : CARRY4

• Low resource usage

○ Reg, LUT, DSP48 ~1%

• Room to add more channels
• PBlock for further time constr.?

Delay line approach : CARRY4

• 4-elements

○ Instantiated to ‘0000’

• Pulse goes in

○ ‘0000’ flips to ‘1111’

■ Or ‘1110’

• Or ‘1100’

○ Or ‘1000’

■ Or ‘0000’

• Output to FDR block

○ Synchronized

Delay line approach : Bubble Correction

• CARRY4 Bubbles

○ ‘1110’ shows up as ‘1101’

• Fixed with LUT6

○ ‘1101’ to ‘1110’ ○ ‘1001’ to ‘1100’ ○ etc.

Delay line approach: 512 to 9 bit converter

• Split the data, find the zero

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• 512 bits to 3 & 64 bits

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• 64 bits to 3 & 8 bits

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• 8

bits to 3 bits

Delay line approach: Data Output

00 000000000 000000000000000000000 Channel # Sub-Clock Course Counter ~8.4 msec Rollover allowed 8bit / Clock cycle: 16 ns / photon

Delay line approach : Discontinuities

• Different clock regions
• Another gap, same clock

region

• Long line

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• 512 elements

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• ~240 used

Preliminary Data: Differential nonlinearity

(N/No -1) Bin #

Preliminary Data: Time delay between channels

STD ~ 2.35 bins ( ~40 ps)

Time to digital summery

• What did we get?

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• Continuous data stream (sort of)

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• High timing precision (~100 ps)

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• Minimal cross talk (more tests req.)

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• Raw output

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• Cheap

Future development:

• More channels

○ Z-Dock+

• 2D Delay line tests
• Implementation on series 7 FPGA

○ Manual routing via Vivado

Thank you

• Questions ?
• Comments ?