Advanced technology for ILC Calorimeters Readout and DAQ parts - - PowerPoint PPT Presentation

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Advanced technology for ILC Calorimeters Readout and DAQ parts - - PowerPoint PPT Presentation

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Advanced technology for ILC Calorimeters Readout and DAQ parts NANNI Jrme Electronics engineer Laboratoire Leprince Ringuet (France) KEK seminar 2017, December 12 Electronics challenges for ILC ECAL DAQ introduction Electronics

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Advanced technology for ILC Calorimeters

Readout and DAQ parts

NANNI Jérôme Electronics engineer Laboratoire Leprince Ringuet (France) KEK seminar 2017, December 12

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SLIDE 2

DAQ introduction Electronics development Beam tests results Next steps Feeding others projects

2 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Electronics challenges for ILC ECAL

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Preview of prototypes

2nd prototype 6 layers ~ 6k channels 1st prototype 30 layers ~ 10k channels Last prototype 10 layers ~ 10k channels NEW ELECTRONICS DESIGN

Proof of concept

  • Linearity
  • Resolution
  • Sensors
  • Very front-end

Feasibility of design

  • ptions
  • Compactness
  • Granularity
  • Front-end
  • Power pulsing
  • Long SLAB

Construction

  • Integration
  • Environment
  • Services
  • Industrialization
  • Tooling
  • Project org.

Time

3 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Introducing the DAQ

GDCC board Gigabyte Data Concentrator Card DIF board Dectector InterFace SMB board Sweat Main Board FEV board Front End Board CCC board Clock and Control Card Calicoes ASU board Active Sensor Unit

wafers

SLAB

nanni@llr.in2p3.fr - KEK seminar - 2017December12 4

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Calicoes

  • Highly modular and

distributed

  • Control the Ecal

electronics but also the peripheral devices (Power supply, pulse generator,…)

  • Provides a high level

state machine for final user

  • Scripting language

(Python)

  • Good stability

Global control-command architecture

nanni@llr.in2p3.fr - KEK seminar - 2017December12 5

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SLIDE 6

Calicoes

Documentation: http://llr.in2p3.fr/sites/pyrame/calicoes/documentation/index.html

Load connectivity Allocate memory structures Reset device Load configuration Configure devices Synchronize clocks Power on high voltage Start acquisition signals Destroy memory structures Power off high voltage Close connections Stop acquisition signals Flush files

nanni@llr.in2p3.fr - KEK seminar - 2017December12 6

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GDCC (Gigabyte Data Concentrator Card) CCC (Clock and Control Card)

  • Until 8 HDMI connections
  • Synchronize all sub-systems
  • Distribute asynchronous

trigger/busy signals

  • Capable to distribute clock

50MHz

CCC Board Able to connect 7 DIF

  • Base on Xilinx Spartan XC6SLX75
  • Marvell component for Ethernet

GEMAC

DIFs Links (Protocol fsm ser-des 8b/10b)

ETHERNET

TO DIF

CCC interface

MARVELL

FPGA

MCLK TRIG

Main Interface (based on several FSM)

GDCC

nanni@llr.in2p3.fr - KEK seminar - 2017December12 7

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SLIDE 8

DIF (Detector InterFace to the DAQ)

Goal: connect the detector to control and DAQ system by serial link synchronous to 40MHz.

  • Condition signals to VFE chips
  • Configuration
  • Readout
  • Generate clock 2.5MHz for ReadOut
  • Get information like board status,

firmware version … Able to read several thousands of detector channels up to 13000. Able to read different chips for many experiments in our laboratory.

nanni@llr.in2p3.fr - KEK seminar - 2017December12 8

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SMB (Sweat Main Board)

Goal: condition signals for VFE chips, power supply and clock integrity.

Buffer to drive the clocks 40MHz and 2.5MHz Regulator for Analogue and Digital power supply Big capacitance (300mF) to absorb the dynamic power supply current, design for 1 ms acquisition in the barrel. DIF connector FEV connector

9 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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FEV board (Front End Board)

FEV board (top view) FEV board (bottom view) 16 Skiroc2 chip 1024 pixels

  • Read energy of 1024 pixels
  • Slow Control for 16 Skiroc2
  • Readout for 2 partitions of 8 chips
  • 2 power supply (analogue & digital)
  • 16 layers

Glued wafers

10 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Pedestal MIP

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Skiroc chip

  • SILICON SENSORS (325µm

thick) : 26000e-/MIP

  • Cdetector estimated 9pF +

10pF for PCB pad’s

  • PIN diode leakage up to

10nA / channel

  • Ultra low power

consumption (to Minimize cooling)  25 µW/ch with Full Power Pulsing

  • 1 MIP = 4fC
  • 64 channels
  • 250 pads
  • Technology: AMS SiGe 0.35µm
  • Size: 65mm²
  • Very low noise: 2500e- (0.4fC)
  • Dynamic range: 0.4fC  10pC

SKIROC: Silicon Kalorimeter Integrated Read Out Chip

11 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Skiroc chip

rms noise= 5.3 mV ie 1/9 MIP  S/N>9

DC PreAmplifier SKIROC2 1,92 1,93 1,94 1,95 1,96 1,97 1,98 1,99 2 2,01 2,02 10 20 30 40 50 60 Channel DC (V)

<>=1.969 V rms=1.5 mV

Scurves vs threshold

Preamplifier DC level uniformity

Fast shaper noise studies

Pedestal=167 DAC Units 1 Mip ≈4 fC = 20 DAC Units Noise= 2 DAC Units

12 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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SLIDE 13

First tests of ASU bench

There is a specific bench to test FEV board before gluing. Possibility to place a wafer, a mechanic interface and the FEV board. Goal: verify all chip answered, pcb as no shortcut. Also, it’s interesting to estimate noise on each chip.

13 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Scurves, noisy channels

Instead activated all channel, run 8 by 8. Reduce effect of crosstalk. Uniform noise around 220-240uDAC. Reproducible measure in time.

Number of hit Trigger (uDAC)

Masked channel

Number of hit Trigger (uDAC)

After masking channel

Trigger threshold reduced.

14 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Introduce short SLAB

Aluminium cover Thermic layer (copper) DIF board (Detector InterFace) SMB board (Sweat Main Board) FEV board (Front End Version) High Voltage kapton Carbon structure in U

Goal: first studies to improve design.

  • Be able to detect a MIP (Minimum Ionization Particle)
  • Configure all chip compare to noise
  • Have adapted signals for clock and control
  • Get a S/N > 10
  • Read raw data in few ms.

15 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Short SLAB

Get a final layer design include chips, PCB, wafer … Thickness of electronics < 4mm (half alveolar size)

Kapton interconnector HV connector

16 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Last prototype

Compact detector Include up to 10 layers Possibility to place Tungsten between each layer Connect each power supply by a front panel. Auto-masking of noisy channels: Every layers are adjusted in laboratory with optimize scripts. 10 layers adjusted in 3h !!!

17 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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Test beam 2017 @DESY

18 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Excellent results, S/N~20 better than 2015.

Test beam performance presentation: https://indico.cern.ch/event/629521/contributions/2703010/

Concept is validate  next step LONG SLAB

Pedestal position dispersion for all channels (~6 ADC) S/N ratio for all SLABS S/N = 20 ; Dispersion = 7,8%

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SLIDE 19

Event Display

19 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Compact shower + “cosmic” Shower (event layer/layer)

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ILD Slab (for final detector)

For ILD 8 to 12 ASU / layer  Layer length = 2.2 meters Many challenges:

  • Interconnection solution
  • Kapton
  • Connector
  • Propagate signal on 3 meters
  • Clock (delay, load, attenuation, …)
  • Control signals
  • ReadOut (data integrity, amount of data)
  • Power distribution ?
  • Power tree
  • cross board
  • Mechanical structure
  • Design with minimize distortion
  • Weigh
  • Transportation

20 nanni@llr.in2p3.fr - KEK seminar - 2017December12

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12 ASU full equipped of wafer 120k€ Need to make physics with less cost Use mini wafer (4x4 pixels instead of 16x16)

Alpha source put under the long slab for physics

21 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Scurves analysis for baby wafer glue on long slab

ILD Slab (for final detector)

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SLIDE 22

22 nanni@llr.in2p3.fr - KEK seminar - 2017December12

New mechanical structure, able to receive 12 ASU  Total length 3m System to place ASU on structure with 3d printed

ILD Slab (for final detector)

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SLIDE 23

CALICE TO WAGASCI

Location: J-PARK neutrino beam, JAPAN Physics goal: Cross section ratio measurement between H2O/CH for charged-current interaction with different Neutrino energy ranges.

23 nanni@llr.in2p3.fr - KEK seminar - 2017December12

40 MPPC 40 ASU 2 DIF

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SLIDE 24

CALICE TO HGCAL CMS

SMB+FEV board DIF board GDCC board

24 nanni@llr.in2p3.fr - KEK seminar - 2017December12

Base on Calice design: 2 pcb layers

  • read out: 4 chip

SKIROC2cms, 4x32 channels

  • FPGA: ALTERA MAX10
  • sensor (200µm, 6” silicon

wafer)

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Summary

25 nanni@llr.in2p3.fr - KEK seminar - 2017December12

 Electronics and instrumentation department of LLR develop many prototypes

(conception, production and tests), with high technology and good performances. The results of ILD Slab in the next test beam will shows the ability to instrument 2.2 meters active layer (readout, clock, power, data integrity, …).

 LLR DAQ is generic and adapt for many experiments, local, international

(HGCAL CMS) and with Japan (T2K WAGASCI) on innovative and complex projects of detector.

 LLR able to solve Electronics, DAQ, instrumentation Challenges, in a context of

international project with R&D phase, tests definition, proposal solutions. …