AICP AURA Intelligent Co-Processor Jim Austin Advanced Computer - - PowerPoint PPT Presentation

aicp aura intelligent co processor
SMART_READER_LITE
LIVE PREVIEW

AICP AURA Intelligent Co-Processor Jim Austin Advanced Computer - - PowerPoint PPT Presentation

AICP AURA Intelligent Co-Processor Jim Austin Advanced Computer Architectures Group, University of York Cybula Ltd. AICP project Concerted action with FAR (costs and people shared) Started 1 August 2003 for 2 years. AICP


slide-1
SLIDE 1

AICP – AURA Intelligent Co-Processor

Jim Austin Advanced Computer Architectures Group, University of York Cybula Ltd.

slide-2
SLIDE 2

AICP project

  • Concerted action with FAR (costs and

people shared)

  • Started 1 August 2003 for 2 years.
  • AICP Collaborators

– Cybula Ltd. – University of York

slide-3
SLIDE 3

People

  • University of York

– Prof. Jim Austin , Academic manager – Mike Weeks, Technical Lead – Mike Freeman, Technical and Amadeus link

  • Cybula

– Dr. Sujeewa Alwis, Commercial manager

slide-4
SLIDE 4

Motivation

  • Need low cost, embeddable pattern match

engine

  • Many applications could benefit from this –

face recognition, text matching, signal analysis

  • Cybula/UofY AURA technology has many

applications already

slide-5
SLIDE 5

Aims

  • To build an embeddable AURA core.

– Use the existing PRESENCE II card as a platform. – Develop

  • AURA graph matcher – for face recognition
  • AURA CMM core

– Support implanting the FAR application IP

slide-6
SLIDE 6

Technology

Cybula PRESENCE II Uses Vertex FPGA Large on board memory PCI based Basis of Cybulas FaceEnforce system

slide-7
SLIDE 7
slide-8
SLIDE 8

AURA core – The CMM Bit 1 2 3 4 5 6 7 8 Bit 1 Bit 7 Bit 2 Bit 4

slide-9
SLIDE 9

The Compact Binary Vector Processor - CBV

  • AURA operations are based on

manipulation of binary vectors.

  • Many applications.
  • The CBV implements the instruction set

used to make CMMs etc.

  • Non-binary version also available
slide-10
SLIDE 10

Outline architecture

slide-11
SLIDE 11

Expected performance

  • 4 streams:

– AMD Athlon XP2000+ with 256M RAM

Verses

– Virtex II FPGA, 133MHz

with two streams = 1.27 ms. 3.5 - 6.9 speedup with four streams = 635 us. 7.1 - 13.8 speedup

slide-12
SLIDE 12

Face and graph matcher

  • Graph matcher

– Implemented on DSP to test out core. – FPGA version expected to show significant speed-up – Implement on CBV

slide-13
SLIDE 13

Conclusions

  • DSP core built on PII
  • CBV processor defined and now being

implemented on PII

  • Should fit with FAR development later