An Active GHz Clock Network Using Distributed PLLs Vadim Gutnik and - PowerPoint PPT Presentation

An Active GHz Clock Network Using Distributed PLLs Vadim Gutnik and Anantha Chandrakasan Microsystems Technology Lab Massachusetts Institute of Technology Cambridge, MA

Conventional Clock Distribution H Tree Gclk Routed Tree Grid • Central distribution relies on global matching

Sources of Clock Uncertainty Source Buffers Wires Load • Systematic: passive compensation • Random and dynamic: active compensation

Distributed Clock Generation Oscillators GCLK Phase Detectors • Synchronized clock generated at multiple points

Why Symmetric PLLs? 1 Σ Σ Σ PD PD PD Noise transfer function Ref 1 2 2 Σ Σ Σ log( ω ) PD PD PD Ref

How Many Tiles? 50 Total Skew Clock skew (ps) 40 2cm x 2cm 30 1GHz clock Internal 0.25 µ m 20 Skew Boundary Skew 10 0 1 4 9 16 25 36 49 64 Number of Tiles

Modelock 1 1 2 2 3 4 3 4 Next Phase = current phase - average phase error [Pratt 95]

Is Modelock Avoidable? Linear phase detector: mode lock 1 2 1 1 1 3 2 3 2 3 2 3 1 θ 2 Desired phase detector 2 1 1 θ 1 1 3 2 3 2 3 2

Nonlinear Error Summing Phase-detector output current Phase difference θ crit • n from geometry, θ crit = 360/n • Nonlinearity makes modelocked states unstable

Phase Detector - phase In1 In2 Out1 Out2 Out1-Out2 In1 In2 P1 P2 phase Out1 Out2

Phase Detector - frequency In1 In2 Out1 Out2 Out1-Out2 In1 In2 P1 P2 frequency Out1 Out2

Small-Signal Stability + + PD PD PD Reference + + PD PD Φ = − − 1 [ I A A h( )] h( ) A u s s s 1 2 1 j ω Noise transfer function σ log( ω ) s-plane

Loop Filter Pbias In- In+ In+ In- Iout Iout Nbias

Oscillator Input • NMOS-load differential ring oscillator insensitive to supply noise

Large-Signal Acquisition Reference 1.1 Clock Period (nanoseconds) 1.05 1 0.95 0.9 0 1 2 3 4 5 6 7 8 9 10 Simulation time (microseconds)

Full System Hspice Simulation 1.02 Clock Period (nanoseconds) 1.01 1 0.99 0 1 2 3 4 Simulation Time (microseconds) • 16 oscillator network small-signal stable

Results • 2mm chip. 0.35 µ m, single poly triple metal CMOS • 16 oscillators, each 40 µ m x 40 µ m • 24 phase detectors, each 20 µ m x 40 µ m • Total power: 450mW at 3V, 1.3GHz • Jitter < 30ps

Conclusions • Random and time-varying mismatch limit centralized clock distribution • Distributed generation enables shorter distribution • Stable multiple-oscillator PLL demonstrated

Acknowledgements This work is funded by the MARCO Focused Research Center on Interconnects. Vadim Gutnik was partially supported by an Intel Fellowship.