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An Introduction to Electromigration-Aware Physical Design Jens Lienig Dresden University of Technology Dresden, Germany Contents 1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design

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SLIDE 1

An Introduction to Electromigration-Aware Physical Design

Jens Lienig Dresden University of Technology Dresden, Germany

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Introduction: Electromigration

Electromigration (EM): Electromigration is the forced movement of metal ions due to an electric field Ftotal = Fdirect + Fwind Direct action of electric field on metal ions Force on metal ions resulting from momentum transfer from the conduction electrons Al Anode + Cathode

  • Note: For simplicity, the term “electron wind force” often refers to the net effect of these

two electrical forces

<<

E

  • Al+
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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Introduction: Electromigration

Effects of electromigration in metal interconnects:

  • Depletion of atoms (Voids):

→ Slow reduction of connectivity → Interconnect failure

  • Deposition of atoms

(Hillocks, Whisker): → Short cuts => Metal atoms (ions) travel toward the positive end of the conductor while vacancies move toward the negative end

Voids Hillocks

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http://ap.polyu.edu.hk/apavclo/public/gallery.htm

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http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html

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http://www.usenix.org/events/sec01/full_papers/gutmann/gutmann_html

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Metal2 Cu Metal1 Cu e B) Via Depletion Ta/TaN Liner Layer Low κ Dielectric SiN, NSiC Cap Layer Void Metal2 Cu Ta/TaN Liner Layer Low κ Dielectric SiN, NSiC Cap Layer Metal1 Cu e A) Line Depletion Void

Common Failure Mechanisms in Integrated Circuits

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

www.lamel.bo.cnr.it/research/ elettronica/em/rel_res.htm

e e e

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Electromigration and Current Density

Black‘s Equation [1]: Mean time to failure of a single wire due to electromigration

      ⋅ ⋅ = T k E J A MTTF

a n exp

Cross-section-area- dependent constant Activation energy for electromigration Temperature Boltzmann constant Current density Scaling factor (usually set to 2)

  • > Current density is the major parameter in addressing electromigration

during physical design

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1996 (ref) 2006 1 I Iref A Aref J Jref

Why is Electromigration Becoming a Problem?

A I J =

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Why is Electromigration Becoming a Problem? (cont‘d.)

Industry Example (Robert Bosch GmbH): Maximum tolerable current in minimum line width interconnect (Metal1, Al) due to technology scaling

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1996 2000 2001 2002 2003 2004 2005 2006 Imax(Time) / Imax (1996)

Reduction 1996 - 2006: 95 %

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Critical nets

1996 (ref) 2006 1 10 100 # Nets

Uncritical nets

Why is Electromigration Becoming a Problem? (cont‘d.)

# Nets(ref)

Industry Example (Robert Bosch GmbH): Critical nets: Nets with currents near or above maximum tolerable current value

  • > “Manual consideration” of

electromigration problem no longer feasible

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  • Conventional metal wires (house wiring, etc.)

Al ≈ 19,100 A/cm2 Cu ≈ 30,400 A/cm2 … reaching melting temperature due to Joule heating

Maximum Tolerable Current Densities

  • Thin film interconnect on integrated circuits can sustain current densities

up to 1010 A/cm2 before reaching melting temperature, however, at Al ≈ 200,000 A/cm2 Cu (Jmax(Cu) ≈ 5* Jmax(Al) ) ≈ 1,000,000 A/cm2 … it reaches its maximum value due to the occurance of electromigration

Melting temperature limits maximum current densities Electromigration limits maximum current densities

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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  • J. Lienig: An Introduction to Electromigration-Aware Physical Design, ISPD 2006, pp. 39-46

History of Electromigration Research

  • 1861

Discovery of electromigration by M. Gerardin

  • 1950s

First systematic studies of electromigration by

  • W. Seith and H. Wever (Correlation between the direction of

the current flow and the material transport)

  • 1960s

Electromigration is recognized as one of the main reasons for IC failure

  • 1967
  • J. R. Black: Relationship between MTTF (mean time to failure)

and current density and temperature (Blacks law [1])

  • 1975
  • I. A. Blech: Discovery of „immortal wires“ by considering the

product of current density and wire length (Blech length [2])

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Migration in Solid State Materials

Migration in Solid State Materials

Stress Migration

due to mechanical stress

Thermomigration

due to thermal gradient

Electromigration

due to electric field Electrolytic electromigration Solid state electromigration

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Diffusion Processes and Activation Energies EA

Grain: homogeneous lattice of metal atoms Grain boundary: shift in the orientation

  • f the lattice

Triple Point

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Grain Triple Point

Diffusion Processes and Activation Energies EA

Al Al Al Al Al Al Al Al

Grain Boundary Diffusion EA_GRAIN= 0.7 eV (Al) EA_GRAIN= 1.2 eV (Cu)

Al Al Al

Bulk Diffusion EA_BULK= 1.2 eV (Al) EA_BULK= 2.3 eV (Cu)

Al Al

Surface Diffusion EA_SURF.= 0.8 eV (Al) EA_SURF.= 0.8 eV (Cu) Aluminum: Grain Boundary Diffusion + Surface Diffusion Copper: Surface Diffusion

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Special Effects (1): Bamboo Wires Wire Width w [µm] MTTF [h]

I = constant T = constant

wMTTF_min

w < ∅ Grains (Bamboo Wires)

w = ∅ Grains

– + Diffusion

Grain Boundary w

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Special Effects (2): Immortal Wires

– + FN5 FN4 FN3 FN2 FN1

Al+Al+ Al+ Al+ Al+ Al+

Electromigration (EM)

– + FN5 FN4 FN3 FN2 FN1

Al+ Al+ Al+ Al+ Al+ Al+ Al+

Equilibrium between EM and SM if lsegment < “Blech length” – + FN5 FN4 FN3 FN2 FN1

Al+ Al+ Al+ Al+ Al+ Al+

Stress Migration (SM)

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Black‘s Equation [1]: Mean time to failure of a single wire due to electromigration

      ⋅ ⋅ = T k E J A MTTF

a n exp

Cross-section-area- dependent constant Activation energy Temperature Boltzmann constant Current density Scaling factor (usually set to 2)

Maximum Current Density With Regard to Temperature

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Maximum Current Density With Regard to Temperature

Jmax(T) compared to Jmax(Tref = 25 C) [Black1969]

0,01 0,1 1 10 100

  • 40

25 60 80 100 125 150 175

Temperature T [Celsius] Jmax(T) / Jmax(T = 25 C)

MTTF(T) = MTTF(TRef)

Consumer Electronics Automotive Electronics

Example: A temperature rise of 100 K in an Al metallization reduces the permissible current density by about 90 %.

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Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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Which Physical Design Parameters Effect Electromigration?

! Wire widths and via sizes (number of vias) ! Wire shapes, corner bends, via arrangements, etc. ! Current-density-correct pin connections ! Temperature of the chip/interconnect ! Segment length below Blech length

  • Local current density
  • Homogeneity of the current flow
  • Current distribution within

device pins

  • Temperature-dependency of

the maximum current density

  • Immortal wires
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(a) Wire Widths

Minimal wire width wmin:

) ( ) ( ) (

/

T f T J d w f I

ref max Layer AVG RMS

⋅ ⋅ ⋅

) ( ) ( ) ( T f T J d w f I

ref peak Layer peak

⋅ ⋅ ⋅

s min_proces

w

max =

min

w

I wmin dLayer                 − ⋅ ⋅ − = T T T k n E T f

ref ref A

1 exp ) (

Jmax/peak Layer- and current-type dependent maximum permissible current density at reference temperature Tref IRMS/AVG Current (rms, avg, peak) Ipeak T Working temperature Tref Reference temperature f(w) Grain-size-dependent width scaling factor wmin_process Process-dependent minimum wire width n Scaling factor (n = 2 [1]) EA Activation energy k Boltzmann constant Black‘s law with MTTF(T) = MTTF(Tref)

Temperature scaling f(T), if T ≠ Tref :

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(a) Via Sizes

Minimal number of single vias Nmin per via array:

        ⋅ ⋅ ) ( ) ( ceil

_ /

T f T I s I

ref via max AVG RMS

max =

min

N

Imax_via, Maximum permissible Ipeak_via via current at reference temperature Tref IRMS/AVG Via current (rms, avg, peak) Ipeak s Safety factor (1.1 … 1.2) T Working temperature Tref Reference temperature n Scaling factor (n = 2 [1]) EA Activation energy k Boltzmann constant

        ⋅ ⋅ ) ( ) ( ceil

_

T f T I s I

ref via peak peak

                − ⋅ ⋅ − = T T T k n E T f

ref ref A

1 exp ) (

Black‘s law with MTTF(T) = MTTF(Tref)

Temperature scaling f(T), if T ≠ Tref :

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(b) Homogeneity of the Current Flow: Wire Shapes, Corner Bends

I1 I2 I1 + I2

Inhomogeneous current flow

  • > Avoiding of 90-degree corners, rapid width changes, etc.

min max

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Metal2 Metal2 Metal1 Metal1 min max I I

(b) Homogeneity of the Current Flow: Via Arrangements

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(c) Current-Density-Correct Pin Connections Pin of a DMOS transistor

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(c) Current-Density-Correct Pin Connections

? ? ? ? ? ? ? ? ? ? ?

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(c) Current-Density-Correct Pin Connections

2 mA 0.5 mA 0.5 mA 1 mA 1 mA 2 mA 3 mA

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Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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Electromigration-Aware (Analog) Physical Design Flow

Circuit Simulation Schematic Partitioning + Floorplanning Placement Current-Driven Routing Current-Density Verification Physical Design Electromigration- Robust Design

EM Violations

Current-Driven Layout Decompaction Start

No Yes

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Electromigration-Aware (Analog) Physical Design Flow

Circuit Simulation Schematic Partitioning + Floorplanning Placement Current-Driven Routing Current-Density Verification Physical Design Electromigration- Robust Design

EM Violations

Current-Driven Layout Decompaction Start

No Yes

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Current-Driven Routing

Goals:

  • Routing with current-correct wire widths and via sizes
  • Minimization of wire area

Major steps:

  • 1. Concurrent wire planning and segment current determination
  • 2. Calculation of wire widths and via sizes
  • 3. Two-point detailed routing with provided wire widths and via sizes
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Cyclic Conflict in Topology and Current Flow Determination

T1 T2 T3 T4

  • 2 mA

1 mA

  • 3 mA

4 mA

T1 T2 T3 T4

  • 2 mA

1 mA

  • 3 mA

4 mA 1 mA 3 mA 2 mA 2 mA

requires Complete net topology... Current flow within net segments … requires

  • > (1) Wire planning

(2) Detailed routing

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Floorplanning Placement Routing Schematics Current-Density Verification Topology Planning (Area Minimization) Pin Connections Check Detailed Routing of Two- Point Connections Calculation of Wire Widths and Via Sizes Current-Driven Routing: Algorithm Current-Driven Routing Routing Tree Path Widths Wire Planning Current Characterization DRC & LVS Fabrication Violations

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Current-Density Verification

Circuit Simulation Schematic Partitioning + Floorplanning Placement Current-Driven Routing Current-Density Verification Physical Design Electromigration- Robust Design

EM Violations

Current-Driven Layout Decompaction Start

No Yes

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Goal:

  • Automatic verification of actual current densities within arbitrarily

shaped layout structures: Major steps:

  • 1. Determination of maximum current densities in each layer
  • 2. Calculation of actual current densities within layout structures
  • 3. If actual current density exceeds maximum value:

mark violating areas and violation degrees

Current-Density Verification

JWire/Via (T, Layer) ≤ JMax (T, Layer)

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Pin and port verification Selection of critical nets Detailed FEM analysis

  • f critical nets

Visualization of errors

Floorplanning Placement Current-Driven Routing Schematics DRC & LVS Fabrication Current-Density Verification Violations Current-Density Verification: Algorithm Current Characterization

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  • 1. Assignment of current values

at device pins and net ports

  • 2. Layout segmentation into

finite elements (triangles)

  • 3. Calculation of the electric

potential field ϕ(x,y) using FEM

  • 4. Calculation of current density J
  • ut of potential field gradient

J=-1/ρ • grad(ϕ(x,y))

ϕ1 ϕ3 ϕ2

  • 5. Comparison of calculated

current density in every finite element with its maximum permissible value

  • 6. Visualization of the violating

areas

Detailed FEM Analysis of Critical Nets

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Current-Density Verification

Current-density violations within via array Current-density violations within interconnect

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Current-Density Verification

DRC errors: Current density violation in Metal_1 (>=20%, <50%)

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min max

I I

Current-Density Visualization

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Current-Driven Layout Decompaction

Circuit Simulation Schematic Partitioning + Floorplanning Placement Current-Driven Routing Current-Density Verification Physical Design Electromigration- Robust Design

EM Violations

Current-Driven Layout Decompaction Start

No Yes

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Goals:

  • Post-routing adjustment of layout segments according to

their actual current density

  • Homogenization of the current flow

Major steps:

  • 1. Current-density verification
  • 2. Calculation of wire widths and via sizes according to actual currents

in violating net segments

  • 3. Addition of support polygons
  • 4. Layout decompaction

Current-Driven Layout Decompaction

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Floorplanning Placement Current-Driven Routing Schematics DRC & LVS Fabrication Current-Density Verification Current-Driven Layout Decompaction: Algorithm

Violations?

Layout Decomposition Wire and Via Array Sizing Addition of Support Polygons Layout Decompaction Current-Driven Layout Decompaction

No

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(1) Routed net Current-Driven Layout Decompaction: Example

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(2) Current-density verification Current-Driven Layout Decompaction: Example

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Actual current in net segment?

(3) Calculation of currents within violating net segments Current-Driven Layout Decompaction: Example

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Width calculation

(4) Calculation of wire widths and via sizes according to actual currents Current-Driven Layout Decompaction: Example

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(5) After layout decompaction

Support polygons Extended wires and vias

Current-Driven Layout Decompaction: Example

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Contents

1 Introduction 2 Electromigration Issues 3 Electromigration-Dependent Design Parameters 4 Physical Design Methodologies Addressing Electromigration

  • Current-Driven Routing
  • Current-Density Verification
  • Current-Driven Decompaction

5 Summary

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Summary

  • Electromigration: migration of atoms due to momentum transfer from

conduction electrons

  • Al: grain boundary diffusion, Cu: surface diffusion

! Electromigration is becoming a design problem due to increased current densities related to IC down-scaling Technology solutions: (1) Cu instead of Al -> Jmax(Cu) ≈ 5* Jmax(Al) (2) Bamboo structures, Blech length, … Physical design solutions: (1) Current density (2) Temperature ! Model: Black‘s law [1] (MTTF of interconnect and its relationship to current density and temperature)

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Summary (2)

  • Two methodologies for current-density correct interconnect generation:
  • Current-driven routing
  • Solving the cyclic topology/current problem via two-step approach:

wire planning and subsequent two-point detailed routing

  • Current-driven layout decompaction
  • All currents are known (no cyclic topology/current problem)
  • Requires current-density verification and decompaction tool
  • Current-density verification
  • Verification of arbitrarily shaped custom circuit layouts
  • Incorporates thermal simulation data

! Current-density verification must be an integral part of any future design flow

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References

[1] Black, J.R. : “Electromigration - A brief survey and some recent results”;

  • Proc. of IEEE Reliability Physics Symposium, Washington D.C., 1968.

[2] Blech, I.A. : “Electromigration in thin film aluminium films on titanium nitride”; Journal of Applied Physics, Vol. 47, No. 4, 1976. [3] Maiz, J.A.: “Characterization of electromigration under bi-directional (BC) and pulsed unidirectional (PDC) currents”; Proc. of IEEE-International Reliability Physics Symposium, pp. 220-223, 1989. [4] Lienig, J., Jerke, G., Adler, Th.: “Electromigration avoidance in analog circuits: two methodologies for current-driven routing”; Proc. of the 7th Asia and South Pacific Design Automation Conference, IEEE Press, Bangalore, India, January 2002. [5] Lienig, J., Jerke, G.: “Current-driven wire planning for electromigration avoidance in analog circuits”; Proc. of the 8th Asia and South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, pp. 783-788, 2003. [6] Jerke, G., Lienig, J.: “Hierarchical current density verification in arbitrarily shaped metallization patterns of analog circuits”; IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no.1, pp. 80-90, Jan. 2004. [7] Jerke, G., Lienig, J., Scheible, J.: “Reliability-driven layout decompaction for electromigration failure avoidance in complex mixed-signal IC designs”;

  • Proc. of the 41st Design Automation Conference, San Diego, CA, pp. 181-184, 2004.

[8] Adler, T., Barke, E.: “Single step current driven routing of multiterminal signal nets for analog applications”; Proc. of Design, Automation and Test in Europe (DATE),

  • pp. 446-450, 2000.