Application of CADP to Hardware Validation Abderahman KRIOUILE and - - PowerPoint PPT Presentation
Application of CADP to Hardware Validation Abderahman KRIOUILE and Massimo ZENDRI STMicroelectronics Forum Mthodes Formelles "Le Model-Checking en action" Toulouse, France, Oct 2014 Agenda 2 20 years of Hardware Validation
STMicroelectronics
Forum Méthodes Formelles "Le Model-Checking en action" Toulouse, France, Oct 2014
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Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
High-level Low-level
On-Chip level Asynchronous logic Supercomputers Multiprocessor
Application of CADP to Hardware Validation
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15/10/2014
CC-NUMA SCSI-2 Polykid NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
Powerscale
based on PowerPC microprocessors used in Bull’s Escala servers and workstations
Application of CADP to Hardware Validation
Asynchronous logic
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15/10/2014
CC-NUMA SCSI-2 Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
Polykid
based on PowerPC
Application of CADP to Hardware Validation
Asynchronous logic
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High-level Low-level
CC-NUMA Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
SCSI-2
protocol
priorities (SCSI numbers)
reported by Bull
Application of CADP to Hardware Validation
Asynchronous logic
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CC-NUMA SCSI-2 Polykid Powerscale FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
NovaScale/FAME
based on Intel's Itanium-2
asynchronous parts
Application of CADP to Hardware Validation
Asynchronous logic
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
STBus SoC
SoCs
Application of CADP to Hardware Validation
Asynchronous logic
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
FAME2
distributed shared memory
protocol
prediction
Application of CADP to Hardware Validation
Asynchronous logic
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Supercomputers Multiprocessor
High-level Low-level
DES
concurrently and synchronize via handshake protocols
communication delays
Application of CADP to Hardware Validation
Asynchronous logic
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC xSTream STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
FAUST/MAGALI
cating Hardware Processes) model
Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
xSTream
dataflow architecture
multimedia streaming applications
measures:
utilization
Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
Blitter Display
implementing BLIT (Block Image Transfer) and numerous graphical operators
Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
2D Mesh NoC
end-to-end communication
Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display AMBA ACE SoC Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
Platform2012
executable sub-tasks (same code, different data)
tasks in only few clock cycles
Application of CADP to Hardware Validation
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CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 AMBA ACE SoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
Utah NoC
link faults
Application of CADP to Hardware Validation
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15/10/2014
CC-NUMA SCSI-2 Polykid Powerscale NovaScale/FAME FAME2 DES Blitter Display Platform2012 Utah NoC FAUST/MAGALI xSTream STBus SoC 2D Mesh NoC
On-Chip level Asynchronous logic Supercomputers Multiprocessor
High-level Low-level
AMBA ACE SoC
cache coherency standard
box SoC for multiple Ultra HD
Application of CADP to Hardware Validation
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Application of CADP to Hardware Validation
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(LOTOS, LNT, etc.)
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FORTE'96 [Chehaibar-Garavel-Mounier-Tawbi-Zulian-96]
IWTCS'98 [Kahlouche-Viho-Zendri-98]
MEMOCODE’03 [Wodey-Camarroque-Baray-et-al-03]
Application of CADP to Hardware Validation
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ASYNC’07 [Salaum-Serwe-Thonnart-Vivet-07]
MEMOCODE’09 [Garavel-Helmstetter-Ponsini-Serwe-09]
FMICS’11 [Lantreibecq-Serwe-11]
FMICS’13 [Kriouile-Serwe-13]
FMICS’14 [Zhang-Serwe-Wu-et-al-14]
Application of CADP to Hardware Validation
LOTOS/LNT model
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IWTCS'98 [Kahlouche-Viho-Zendri-98]
STTT’01 [Garavel-Viho-Zendri-01]
Application of CADP to Hardware Validation
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SPIN'04 [Garavel-Mateescu-04]
Science of Computer Prog. [Lantreibecq-Serwe-14]
Application of CADP to Hardware Validation
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Application of CADP to Hardware Validation
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FME'02 [Garavel-Hermanns-02]
QuEST’09 [Chehaiber-Zidouni-Mateescu-09]
CAV’09 [N.Coste’PhD thesis]
IPDPSW’10 [Foroutan-Thonnart-Hersemeule-Jerraya-10]
Application of CADP to Hardware Validation
evaluation
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