Area and Time Tradeoffs in FPGAs Examining the concept of area/time - - PowerPoint PPT Presentation

Area and Time Tradeoffs in FPGAs

Richie Ung Trang (z5061606) Harry Gougousidis (z5159917) Henry Veng (z5113239)

Examining the concept of area/time tradeoffs in FPGA design, pattern matching, and Advanced Encryption Standard (AES)

Presentation Overview

• 1. Background
• 3. AES
• 6. Prototype
• 5. Timeline
• 4. Pattern Matching

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• 2. FPGA Design Tradeoffs

Motivation – Diverse Set of Vendors and Boards

• 1. Background

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A market full of FPGAs with differing cost, performance, and consumption requirements. What are the circuit and architectural design attributes of an FPGA that trade

• ff area and speed?

What are the magnitude of these tradeoffs?

Motivation – Narrowing Gap with ASICs

• 1. Background

4

Learning which attributes affect area/time performance will help FPGAs narrow the gap to ASICs in one area. ~35x ~14x ~1/3

Measuring Time in FPGA Design

• 1. Background

5

Simple Approach: Take a set of circuits that make up the critical paths in a collection of benchmark designs to create a performance metric.

Measuring Time in FPGA Design

• 1. Background

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Model Approach: Use the shortest register to register path within the FPGA that contains all unique components. Use a weighted average based on the frequency each component is tested at during a critical path test.

Measuring Area in FPGA Design - SRAM

• 1. Background

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The SRAM is the single most frequently repeated structure in the FPGA. Significant effort is therefore spent optimizing the layout of the 6 transistors that make up a single bit.

Transistor Model

Measuring Area in FPGA Design – SRAM

• 1. Background

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Minimum Transistor Width Model

Space/Time Tradeoff Results in FPGA Design

• 1. Background

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Some Comparative Results

PATTERN MATCHING ON FPGA

By Henry Veng

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Background

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Pattern Matching:

• Process of finding a particular

substring (pattern) within a string

Background

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Uses:

• Gene detection in DNA sequences
• Network Intrusion Detection

Systems(IDS)

Background

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Network IDS Requirements:

• Many patterns against one string
• Support as many rules as possible
• Real time
• Internet speeds

Design

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Overview

• Custom implementation of KMP
• Pipelining within pattern matching

units

• Linear array of pattern matching units

Design

15

KMP Algorithms Characteristics:

• Allows input stream to keep moving

forward

• Good worst-case performance

Design

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Custom KMP Pattern Matching Units:

• Two comparators and a buffer
• Buffer of specific size
• Allows one character per clock cycle

throughput

Design

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Pipelining within Units

• Two patterns sharing the same

combinational circuit

• Matching occurs out of phase
• Allows a lower hardware per pattern

ratio

• Allows an increase in clock speed

Pattern Memory Pattern Memory Combinational Circuit

Design

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Linear Array of Pattern Matching Units:

• Input characters must pass through all

units

• Different patterns loaded in different

units

• Allows parallelisation
• Units are quickly reconfigurable

Area/Time Tradeoff

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Metrics:

• Time: Throughput (Mb/s, Gb/s, etc)
• Area: Logic cells used

Area/Time Tradeoff

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Area/Time Tradeoff

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U/Crete:

• Very high throughput (10.8Gb/s) but

high area cost (532 logic cells/32- char unit)

• Achieved through hardwired

comparators and replicated 4 times

• Supports ~100 rules and

reconfiguration is very slow

Conclusion

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Different design decisions can affect/the area time tradeoff

By Harry Gougousidis

Advanced Encryption Standard

FPGAs and Encryption

• FPGAs allow more flexibility and

potential speedup than most hardware

• ptions.
• Maximising data throughput requires

balancing resource utilisation and time delays.

• Encryption takes significant time to

process data and is often required

• n devices with small resource pools.

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Introduction to AES

• Cryptography is popular on

hardware due to relatively simple

• perations in a highly parallelisable

way.

• Fixed data block length, fixed

amount of transformations, single key for encryption and decryption.

• Four transformations operations: a

lookup table, matrix multiplication, byte shifting, and key XORing.

AES Enhancements

• Inter-round: unrolling, pipelining
• Intra-round: pipelining, partitioning

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AES Implementations

• Most transformations are

Configurable Logic Blocks.

• Byte substitution can be BRAM,

Distributed RAM or CLBs to different effect.

• Conventional processors run

significantly worse than FPGAs.

• ASICs run slightly faster than

FPGAs but lack the flexibility.

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Time/Area Tradeoffs

• Fully unrolled has high area cost

but large performance increase.

• Pipelining and partitioning has a

large increase in performance for minimal area increase. Can increase latency by a lot.

• Performance can be calculated

via maximum throughput (data per second), latency (time until first packet), and efficiency (throughput per slice count).

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Paper Results

• Optimal choice depends on user

metrics.

• Unrolling performed well but had

poor efficiency.

• Distributed RAM performed better

than block RAM but block RAM was much better at efficiency.

• Transformation partitioning

alone gave significant improvement efficiently.

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Thanks for listening! Question Time

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