Benefits of Asynchronous Control for Analog Electronics: Multiphase - - PowerPoint PPT Presentation

Benefits of Asynchronous Control for Analog Electronics: Multiphase Buck Case Study

Danil Sokolov, Vladimir Dubikhin, Victor Khomenko, David Lloyd

Newcastle University, UK

Outline

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• Motivation
• Basic buck converter
• A4A design flow
• A2A components
• WORKCRAFT design automation
• Design of multiphase buck converter
• Experimental results

Motivation: Little digital control for analog electronics

3 / 21 A2D D2A infrastructure digital analog sensor/timing/energy time bands design automation scope for

Legend: IP cores (big digital)

level shifters sensors synchronisers

sanitisers

power converters

control for analog layer (little digital)

slow fast local

• Analog and digital electronics are becoming more intertwined
• Analog domain becomes more complex and itself needs digital control

Motivation: Power electronics context

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• Efficient implementation of power converters is paramount
• Extending the battery life of mobile gadgets
• Reducing the energy bill for PCs and data centres

(5% and 3% of global electricity production respectively)

• Need for responsive and reliable control circuitry
• Millions of control decisions per second for years
• An incorrect decision may permanently damage the circuit
• Need for EDA (little digital vs big digital design flow)
• RTL flow is optimised for synchronous data processing
• Ad hoc asynchronous solutions are prone to errors and cannot be verified

Basic buck converter

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V_nmos V_pmos I_0

R_load PMOS NMOS

I_max gp_ack

• c

uv zc gn_ack gp gn

• ver-current

zero-crossing

analog buck digital control

V_ref

under-voltage

Phase diagram specification:

UV UV OC I_max

Current no ZC late ZC

OC

early ZC

PMOS OFF ZC PMOS OFF NMOS ON NMOS OFF ZC N M O S O F F PMOS ON NMOS OFF NMOS ON PMOS OFF P M O S O N UV OC

Time

N M O S O F F P M O S O N I_0

Buck conditions:

• under-voltage (UV)
• ver-current (OC)
• zero-crossing (ZC)

Operating modes:

• no zero-crossing
• late zero-crossing
• early zero-crossing

Basic buck converter: Synchronous design

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RTL description:

module control (clk, nrst, oc, uv, zc, gp_ack, gn_ack, gp, gn); . input clk, nrst, uv, oc, zc, gp_ack, gn_ack; .

• utput reg gp, gn;

. always @(posedge clk or negedge nrst) begin . if (nrst == 0) begin . gp <= 0; gn <= 1; . end else case ({gp_ack, gn_ack}) . 2’b00: if (uv == 1) gp <= 1; else if (oc == 1) gn <= 1; . 2’b10: if (oc == 1) gp <= 0; . 2’b01: if (uv == 1 || zc == 1) gn <= 0; . endcase . end .endmodule

Design Compiler synthesis result:

RB CK D Q SB CK D Q

clk nrst gp_ack gn_ack

• c

uv zc gp gn

• Asynchronous inputs need to be synchronised (latency penalty)
• If clock is slow, the control is unresponsive to the buck changes
• If clock is fast, it burns energy when the buck is inactive

Basic buck converter: Asynchronous design

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Formal specification: Hazard-free implementation:

• Formal specification using Signal Transition Graphs – similar to Petri nets
• Verifiable hazard-free implementation – correct for any gate delays
• Prompt reaction time to the buck changes – latency of a complex gate

Asynchronous control for Analog electronics (A4A) design flow

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informal design intent (waveforms, phase diagrams) architectural decomposition and component formalisation formal specification of components (signal transition graph) logic synthesis & technology mapping (Petrify, Punf, MPSat) verification report (violation traces) reachability report (hazard traces) signoff report (timing violations) hazard-free components (Verilog netlist) system integration (Workcraft) little digital asynchronous controller (Verilog netlist) sanity check (Punf, MPSat) functional verification (PComp, Punf, MPSat) design concepts timing verification (PrimeTime) gate library A2A interfaces

specification and synthesis verification and validation libraries and design guidelines

manual effort

• ffline testing features

and place & route conventional design flow

Library of analog-to-asynchronous (A2A) interface components

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• Interface analog world of dirty signals
• Provide hazard-free sanitised digital signals
• Basic A2A interface components
• WAIT / WAIT0

– wait for analog input to become high / low and latch it until explicit release signal

• RWAIT / RWAIT0

– modification of WAIT / WAIT0 with a possibility to persistently cancel the waiting request

• WAIT01 / WAIT10

– wait for a rising / falling edge

• Advanced A2A interface components
• WAIT2

– combination of WAIT and WAIT0 to wait for high and low input values, one after the other

• WAITX

– arbitrate between two non-persistent analog inputs

• WAITX2

– behaves as WAITX in the rising phase and as WAIT0 in the falling phase

WORKCRAFT design automation – http://workcraft.org/

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Multiphase buck converter

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R_load

V_nmos V_pmos V_nmos V_pmos

analog buck

PMOS NMOS PMOS[N] NMOS[N]

digital

• c

zc

• cN

uv zcN gn_ackN gn_ack gp gp_ack gn gp_ackN gpN gnN hl

• ver-current

I_0 (I_neg) I_max (I_0) I_max (I_0) I_0 (I_neg) V_ref

zero-crossing under-voltage

V_min

high-load

V_max

• ver-voltage
• v

basic converter

control

multiphase converter

• Phases – pairs of power regulating transistors
• Each phase operates as a basic buck
• Phases are activated sequentially
• Active phases may overlap
• More operating modes
• Over-voltage (OV) – sink energy excess
• High-load (HL) – boost the power
• Transistor min ON times
• PMOS transistor: PMIN delay
• NMOS transistor: NMIN delay
• PMOS at first cycle: PMIN+PEXT delay

Multiphase buck converter: Synchronous control

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• Two clocks: phase activation (slow) and sampling (fast)
• Need for multiple synchronizers (grey boxes) – latency overheads, risk of metastability
• Conventional RTL design flow for PHASE_ACTIVATOR and SYNC_PHASE_CTRL components

Multiphase buck converter: Asynchronous control

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• Token ring architecture, no need for phase activation clock
• No need for synchronisers – all signals are asynchronous
• A4A design flow for ASYNC_PHASE_CTRL component

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Asynchronous phase control

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• analog-asynchronous interfaces
• synthesised hazard-free components

l asymmetric delays elements

Multiphase buck converter: Design of asynchronous components

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• Token control
• Formal specification
• Hazard-free implementation

Experimental results: Simulation setup

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• Verilog-A model of the 4-phase buck
• Control implemented in TSMC 90nm
• AMS simulation in CADENCE NC-VERILOG
• Synchronous design
• Phase activation clock – 5MHz
• Clocked FSM-based control – 100MHz, 333MHz, 666MHz, 1GHz
• Sampling and synchronisation
• Asynchronous design
• Phase activation – token ring with 200ns timer (= 5MHz)
• Event-driven control (input-output mode)
• Waiting rather than sampling (A2A components)

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous redundant switching activity of two clocks

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous unnecessary activation

• f phases

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous resolution time for over-voltage condition

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous recuring

• ver-voltage

condition

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous

• vershoot

after high-load condition

Experimental results: Simulation waveforms

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1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

0.24A

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

0.21A

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

phase

synchronous @ 333MHz asynchronous voltage ripple

Experimental results: Simulation waveforms

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0.43V 1 2 3 4 5 6 7 8 9 10

phase_clk fsm_clk V_load (V) hl uv

• v

act TIME (μs)

3 2 1 3.3V

I_coil (A) 0

0.2 0.1

• 0.1

startup normal load high load normal load

phase

I_coil (A)

0.2 0.1

• 0.1

V_load (V) hl uv

• v

get & !pass

3 2 1 3.3V

startup normal load high load normal load

0.36V

phase

synchronous @ 333MHz asynchronous inductor peak current

Experimental results: Reaction time

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Buck controller HL UV OV OC ZC (ns) (ns) (ns) (ns) (ns) SYNC @ 100MHz 25.00 25.00 25.00 25.00 25.00 SYNC @ 333MHz 7.50 7.50 7.50 7.50 7.50 SYNC @ 666MHz 3.75 3.75 3.75 3.75 3.75 SYNC @ 1GHz 2.50 2.50 2.50 2.50 2.50 ASYNC 1.87 1.02 1.18 0.75 0.31 Improvement over 333MHz 4x 7x 6x 10x 24x

Synchronous buck controllers exhibit latency of 2.5 clock cycles.

Experimental results: Peak current

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3.1 1.8 2.25 4.7 8.2 6.8 5.7

1 2 3 4 5 6 7 8 9 10 100 200 300 400 500 600 700

Coil inductance (μH) Inductor peak current (mA)

100MHz 333MHz 666MHz 1GHz ASYNC

Experimental results: Inductor losses

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3.1 1.8 2.25 4.7 8.2 6.8 5.7

20 40 60 80 100 120 140

Inductor losses (μW)

1 2 3 4 5 6 7 8 9 10

Coil inductance (μH)

100MHz 333MHz 666MHz 1GHz ASYNC

Conclusions

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• A4A design flow is automated in Workcraft framework
• Library of A2A components
• Automatic synthesis of hazard-free circuits
• Formal verification at the specification and circuit levels
• Benefits of asynchronous multiphase buck controller
• Reliable, no synchronisation failures
• Quick response time (few gate delays)
• Reaction time can be traded off for smaller coils
• Lower voltage ripple and peak current
• A4A flow, A2A interfaces, and WORKCRAFT tools are used at Dialog Semiconductor