Boolean Logic Foundations of Global Networked Computing: Building a - - PowerPoint PPT Presentation

Foundations of Global Networked Computing: Building a Modern Computer From First Principles

IWKS 3300: NAND to Tetris Spring 2019 John K. Bennett

This course is based upon the work of Noam Nisan and Shimon Schocken. More information can be found at (www.nand2tetris.org).

Boolean Logic

Boolean Algebra

Some elementary Boolean functions:  Not(x)  And(x,y)  Or(x,y)  Nand(x,y) (functionally complete!)

x y z

0 0 0 0 0 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0

z y x z y x f ) ( ) , , (  

Boolean functions:

 A Boolean function can be expressed using a logic expression, a truth table or a schematic.  Important observation: Every Boolean function can be expressed using And, Or & Not, so, if your function can implement these 3, it is “functionally complete.”

x y Nand(x,y) 0 0 1 0 1 1 1 0 1 1 1 0 x y And(x,y) 0 0 0 0 1 0 1 0 0 1 1 1 x y Or(x,y) 0 0 0 0 1 1 1 0 1 1 1 1 x Not(x) 0 1 1 0

All Boolean Functions of Two Variables How many for n variables?

Boolean Algebra

Given: Nand(a,b), false We can build:

 Not(a) = Nand(a,a)  true = Not(false)  And(a,b) = Not(Nand(a,b))  Or(a,b) = Not(And(Not(a),Not(b)))  Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b)))  Etc. (i.e., any Boolean function) We can prove this!

George Boole, 1815-1864 (“A Calculus of Logic”)

Gate Logic

 Gate logic – a gate architecture designed to implement a Boolean function  Elementary gates:  Composite gates:  Important distinction: Interface (what) VS implementation (how).

Gate Logic

And And Not Or

• ut

a b

Not

Xor(a,b) = Or(And(a,Not(b)),And(Not(a),b))) An (Inefficient) Implementation

Xor a b

• ut

0 0 0 0 1 1 1 0 1 1 1 0 a b out

Interface Claude Shannon, 1916-2001 (“Symbolic Analysis of Relay and Switching Circuits” )

0 0 0 0 1 0 1 0 0 1 1 1 a b out

a b

• ut

power supply

AND gate

power supply

a b

• ut

0 0 0 0 1 1 1 0 1 1 1 1 a b out OR gate

Circuit Implementations

 From a theoretical perspective, physical realizations of logic gates are irrelevant.  From an engineering perspective, physical realizations of logic gates are essential to performance. Diode Transistor Implementation of NAND

Project 1: Elementary Logic Gates

Given: Nand(a,b), false Build:

 Not(a) = ...  true = ...  And(a,b) = ...  Or(a,b) = ...  Mux(a,b,sel) = ...  Etc. - 12 gates altogether.

a b Nand(a,b) 0 0 1 0 1 1 1 0 1 1 1 0

Q: Why these particular 12 gates? A: Since …

 They are commonly used gates  They provide all the basic building

blocks needed to build our computer.

Multiplexor

Proposed Implementation: based on Not, And, Or gates (since we can build all of these from NAND.

a b sel

• ut

Mux

a b sel out 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 1 sel out 0 a 1 b

See Lab Notes: Multiplexors can be used a “function generators.” For example, how might a 4:1 mux be used to generate all possible combinations of two Boolean variables?

• ut

a b

And

a b out 0 0 0 0 1 0 1 0 0 1 1 1

And.cmp

load And.hdl,

• utput-file And.out,

compare-to And.cmp,

• utput-list a b out;

set a 0,set b 0,eval,output; set a 0,set b 1,eval,output; set a 1,set b 0,eval,output; set a 1, set b 1, eval, output;

And.tst And.hdl

CHIP And { IN a, b; OUT ; // implementation missing }

Example: Building an AND Gate

Contract: When running your .hdl on our .tst, your .out should be the same as the book’s .cmp.

Building an AND Gate

• ut

a b

And

CHIP And { IN a, b; OUT out; // implementation missing }

And.hdl Interface: And(a,b) = 1 exactly when a=b=1

Implementation: And(a,b) = Not(Nand(a,b))

• ut

a b

Building an AND Gate

CHIP And { IN a, b; OUT out; // implementation missing }

And.hdl

• ut

Not a b

• ut

Nand

a

in

• ut

x

b

Implementation: And(a,b) = Not(Nand(a,b))

CHIP And { IN a, b; OUT out; // implementation missing }

And.hdl

Building an AND Gate

CHIP And { IN a, b; OUT out; Nand(a = a, b = b,

• ut = x);

Not(in = x, out = out) }

Implementation: And(a,b) = Not(Nand(a,b))

• ut

NOT a b

• ut

NAND

a

in

• ut

x

b

Building an AND Gate

And.hdl

Equation: And(a,b) = Not(Nand(a,b))

• ut

NOT a b

• ut

NAND

a

in

• ut

x

b

Building an AND Gate with LogicCircuit

Building an AND Gate in LogicCircuit

Building an AND Gate in LogicCircuit – NAND Gate First

Building an AND Gate in LogicCircuit – NAND First

How Will We Create the HDL Files?

CHIP Nand { IN a, b; OUT out; PARTS: Nand2 (x1 = a, x2 = b, q = out); }

Building the AND Gate

// This file was generated from LogicCircuit CircuitProject: And // This is beta release code. Please report bugs to jkb@colorado.edu // 1/21/2019 10:21:11 AM /* #83,254,54,183,54,227,48,16,54,71,204,246,252,72,82, 22,179,128,38,52,84,200,39,21,37,135,202,244,64,254, 32,165,13,213,118,124,21,225,106,253,87,42,119,17,226, 38,105,68,136,111,81,74,166,33,253,142,240,176,187,82, 108,81,105,218,101,26,236,174,243,221,147,211,200,167,63, 198,155,149,254,56,20,232,82,22,127,34,80,188,43,207, 14,124,60,172,244,243,50,163,172,143,165,195,81,115,105, 192,89,182,64,75,149,42,189,241,84,52,127,100,119,70, 209,132,210,49,248,200,56,25# */ CHIP And { IN a, b; OUT out; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = U0out, b = U0out, out = out); }

Building the XOR Gate

And And Not Or

• ut

a b

Not

CHIP Xor { IN a,b; OUT out; PARTS: Not(in=a,out=Nota); Not(in=b,out=Notb); And(a=a,b=Notb,out=w1); And(a=Nota,b=b,out=w2); Or(a=w1,b=w2,out=out); }

 … using only NAND gates

A Better XOR Implementation Why is this better?

Building an XOR Gate in LogicCircuit

Create the HDL File

//Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out = out); }

“SaveAsHDL”

Hardware Simulator (Book)

Testing the Xor Gate HDL

How Will We Test These HDL Files?

//Xor.hdl CHIP Xor { IN a, b; OUT; PARTS: Nand (a = a, b = b, out = U0out); Nand (a = a, b = U0out, out = U1out); Nand (a = U0out, b = b, out = U2out); Nand (a = U1out, b = U2out, out =

• ut);

}

“Load Chip”

How Will We Test These HDL Files?

// Xor.tst load Xor.hdl,

• utput-file Xor.out,

compare-to Xor.cmp,

• utput-list a%B3.1.3 b%B3.1.3
• ut%B3.1.3;

set a 0, set b 0, eval,

• utput;

set a 0, set b 1, eval,

• utput;

set a 1, set b 0, eval,

• utput;

“Load Script”

Hardware Simulator (demonstrating XOR gate construction)

test script HDL program

Hardware Simulator

HDL program

HDL program

Hardware Simulator

• utput

file

How Will We Test These HDL Files?

| a | b | out | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

Xor.cmp

| a | b | out | | 0 | 0 | 0 | | 0 | 1 | 1 | | 1 | 0 | 1 | | 1 | 1 | 0 |

Xor.out

If (Xor.out == Xor.cmp)

Testing the Xor gate using the N2T Hardware Simulator

Testing Logic in LogicCircuit

Project Materials: www.nand2tetris.org

Project 1 web site

And.hdl , And.tst , And.cmp files

Project 1 Tips

 Read the Introduction + Chapter 1 (my version) of the book  Download the book’s software suite (if using your own computer)  Download LogicCircuit (my version) (if using your own computer)  Go through the hardware simulator tutorial  Do Project 0.5  Check out the HDL Survival Guide: http://nand2tetris.org/software/HDL%20Survival%20Guide.html

a b c

and and

• r

f(a,b,c)

. . .

Perspective

 Each Boolean function has a canonical representation  The canonical representation is expressed in terms of And, Not, Or  And, Not, Or can be expressed in terms of NAND alone  Thus, every Boolean function can be realized by a standard

programmable logic device (PLD) using NAND gates only

 Mass production  Universal building blocks,

unique topology

 Gates, neurons, atoms, …

a b c

and and

• r

f(a,b,c)

8 and terms connected to the same 3 inputs

. . .

(the on/off states of the fuses determine which gates participate in the computation) single or term connected to the

• utputs of 8 and terms

active fuse blown fuse legend:

PLD implementation of f(a,b,c)= a b c + a b c _ _ _

End Notes: Programmable Logic Device for 3-way functions

a b c

and and

• r

f(a,b,c)

. . .

End Notes: Universal Building Blocks, Unique Topology

Artificial Neuron