BTW03 BTW03 Presented By Stephen Harrison & Peter Collins - - PowerPoint PPT Presentation

Presented By Stephen Harrison & Peter Collins

DESIGN CONSIDERATIONS IN USING 1149.1 AS A BACKPLANE TEST BUS

Pete Collins petec@jtag.co.uk

JTAG TECHNOLOGIES

BTW03 BTW03

2003 International Test Conference

Presented By Stephen Harrison & Peter Collins

PURPOSE

Hierarchical IEEE Std. 1149.1 backplane test access has become increasingly accepted as a test strategy for testing boards/modules within a system environment. The emergence of a variety of 1149.1 system test access devices from a number of silicon vendors now provides designers with more choice. System level architectural requirements dictate what system test access devices should be used.

The purpose of this presentation is to discuss the importance of correctly identifying the system test requirements at the design concept stage so that the

• ptimal system test access architecture is implemented.

This is because:-

Presented By Stephen Harrison & Peter Collins

CONTENT

• Introduction
• System Level Routing Strategies
• Supporting Devices
• Architectural Decisions
• Embedded Vector Delivery
• BIST Sequencer Overview
• Board & System Level BIST Strategy
• Conclusions

Presented By Stephen Harrison & Peter Collins

INTRODUCTION

Implementation of a system level test architecture can be utilised to provide a more flexible test and enhanced diagnostic capability by:-

• Providing a single-point access to multiple scan chains in support
• f design and test partitioning.
• Support a board-to-board interconnect test strategy that will allow

edge connector pin level diagnosis.

• Accommodate system checkout of firmware objects prior to customer

shipment and facilitate field level firmware upgrades.

• Provide a system level infrastructure to exercise embedded test

structures implemented within ASIC’s and FPGA’s.

Presented By Stephen Harrison & Peter Collins

TDI TDO TCK TRST TMS(1) TMS(2) TMS(3) TMS(N)

Board 1 Board 2 Board N Board 3

System Architecture (Star)

Multiple TMS lines significantly increases backplane signalling

Presented By Stephen Harrison & Peter Collins

TDI TDO TCK TRST TMS

Board 1 Board 2 Board N Board 3 Slot Empty

Breaks TDO/TDI Chain

Boundary Scan cannot be performed due to empty slot which breaks the boundary scan chain

System Architecture (Ring)

Presented By Stephen Harrison & Peter Collins

TDI TDO TCK TRST TMS

Board 1

System Access device System Access device System Access device System Access device

Slot ID Slot ID Slot ID Slot ID

Board 2 Board 3 Board N

Backplane access limited to the 5 JTAG control signals + 6 address lines for selecting the board slot ID Each board requires the minimum of a single System Interface device

System Architecture (Multi-drop)

Presented By Stephen Harrison & Peter Collins

Hierarchical Boundary-Scan System Access

• A system level device contains one primary TAP and one or

more secondary TAP’s.

• The local board boundary-scan chains are connected to the

secondary TAP’s.

• The boundary-scan controller is connected to the primary TAP.
• By applying the appropriate system level device protocol, the

primary TAP of the device can access the chains on the secondary TAP’s

Boundary-scan Controller System Access Device

Primary (Global)

TAP1

Secondary (Local)

TAP1 TAP2 TAP3

Presented By Stephen Harrison & Peter Collins

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 1

TDI, TDO, TMS TRST, TCLK & AW

Standard Backplane I/O Slot ID

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 2

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 3

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board n

External JTAG Controller

System Level Configuration External Controller

Presented By Stephen Harrison & Peter Collins

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 1

TDI, TDO, TMS TRST, TCLK & AW

Standard Backplane I/O Slot ID

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 2

ScanBridge

Board ID Register

External Scan Control

Scan Chain 1

Scan Chain 2 Scan Chain 3

Printed Circuit Board 3

ScanBridge & Scan Controller

Board ID Register

External Scan Control

Scan Chain 1

Flash

Scan Chain 2 Scan Chain 3

System Controller Card

ASIC FPGA Up

System Level Configuration Embedded Controller

Presented By Stephen Harrison & Peter Collins

Chipset Solution Providers

Types of System Level Devices

Chipset Features

How many local scan ports are supported ? Does the system test access device support Multidrop access ? Does the system test access device support parking of local scan chains ? Is there provision to access proprietary test signals ? Does the system test access device have a generic pass through capability ? Does the system test access device have the capability to read back the board ID and Revision ?

Chipset Solution Providers

Lattice Semiconductor Multiple Scan Port LSC BSCAN-1 Texas Instruments Scan-Path Linker SN54/74ACT8997 Texas Instruments Addressable Scan Port SN54/74LVT8996 Lattice Semiconductor Scan Path Linker LSC BSCAN-2 National Semiconductor ScanBridge SCANSTA111 Firecron Ltd Gateway Device JTS06 (IP Core or as device) Firecron Ltd Gateway Device JTS03 (IP Core or as device)

Semi-house Name Device

SCANSTA112 ScanBridge National Semiconductor SN54/74ACT8986 Linking Addressable Scan Port Texas Instruments

Presented By Stephen Harrison & Peter Collins

Multidrop Test Configuration

Boundary-scan Controller

Primary Tester TAP1 LSC1 1 2 3 4 LSC2

ScanBridge

(STA111)

Board 1 Board 2 LSC1 LSC2 No Chain

Gateway Device (JTS03)

LSC3 LSC4 No Chain

Gateway Device (JTS03)

MULTIDROP 1 MULTIDROP 2

LSC3

Presented By Stephen Harrison & Peter Collins

Proprietary Test Signal Pass-through

Flash Memory

Primary Scan Port

JTAG Bus LSC 1

Gateway/Bridge MPC8260 Processor

Data Address

cPLD

Control

WE

WE LSC 1

WE Strobe

DSP

WE LSC 2 N/C

WE

ASIC

JTAG Bus LSC 2 JTAG Bus LSC 3 WE LSC 3 N/C

Dependant upon specific board designs it may be necessary to route proprietary test signals from the edge connector to devices within the target local scan chain i.e. passing-through a WE Strobe pulse to optimise flash programming. This can be a generic pass-through capability i.e. input-to-output or dependant on local scan chain selection. This is important when the local distribution of the proprietary signal is to multiple chains and devices.

Presented By Stephen Harrison & Peter Collins

Gateway/Bridge

FPGA’s

Pass/thru Enable

cPLD’s

Pass/thru Sel 0

1 X X HIGHZ 1 1 LSC 3 1 LSC 2 1 LSC 1 P/Thr Enable P/Thr Sel(1) P/Thr Sel(0)

Pass/thru Sel 1

Pass/Thru on LSP 3

Primary JTAG Port

Pass/Thru on LSP 1 Pass/Thru on LSP 2

DSP

1

Transparent Mode

TRANSPARENTn

Vendor specific proprietary programming/emulation tools do not support the protocols necessary to communicate with system access devices. Generic pass-through capability necessary to make the connection between primary JTAG port and LSP transparent by dedicated control pins or specific instruction.

Presented By Stephen Harrison & Peter Collins

How do I Read the Board ID and Revision?

Primary Scan Port

JTAG Bus LSC 1

Gateway/Bridge

cPLD

BOARD_ID Register

16-bit User-definable Register hard-wired to Vcc or GND Depending upon ID code

Gateway devices have an internal 16-bit Register which can be hard-coded by tying device pins to Vcc or GND dependant upon user-defined ID code. This register can be accessed once the Gateway is selected. Alternative devices do not have this utility, subsequently a set LSC on each card within the system will need to dedicate this LSC and 1149.1 compliant device to hard-wire the board ID code and revision i.e. cPLD or Scan buffer.

• The limitations in this alternative method is that board designs are subject

to change due to obsolescence etc. that may change the boundary-scan infrastructure.

Hard-wire unused I/O pins To VCC or GND to provide User-definable ID code

Presented By Stephen Harrison & Peter Collins

Local Scan Chain 3 Local Scan Port 1 Local Scan Port 2

Non-Scan Logic

JTAG Port & Slot ID Primary Board I/O

Plug On Daughter Card Local Scan Port 1 Local Port Chain 3

Daughter Brd I/O

Primary to Daughter board connection tested using Boundary-Scan Primary to Daughter board connection tested using Boundary-Scan

L

• c

a l S c a n P

• r

t 2

JTAG Bridge/Gateway JTAG Bridge/Gateway

Mother/Daughter Card Interconnect Testing

Scan Bridge CONnection File TESTER_CHANNEL TAP1 MULTIDROP1 (JTS03,1,0,TAP1,CASCADE1, TAP3) CASCADE1 (STA111,0,TAP4,TAP5, TAP6) END_CHANNEL Scan Bridge CONnection File TESTER_CHANNEL TAP1 MULTIDROP1 (JTS03,1,0,TAP1,CASCADE1, TAP3) CASCADE1 (STA111,0,TAP4,TAP5, TAP6) END_CHANNEL

Presented By Stephen Harrison & Peter Collins

Slot ID 0 WE Strobe

Back-Plane Signals

Local Scan Port 1

Non-Scan Logic

JTAG Bridge/Gateway

Local Scan Port 1

Non-Scan Logic

JTAG Bridge/Gateway

Slot ID 1

JTAG Port JTAG Port

TDI, TDO, TCK TMS & TRST Back-Plane JTAG Signals

Hierarchical Interconnect Test Configuration

(Parking of Local Scan Chains)

Local Scan Port 2 Local Scan Port 2 Local Scan Port3 Local Scan Chain 3

Presented By Stephen Harrison & Peter Collins

Vcc

TRST0 TDO0 TMS0 TCK0 TDI0

BRIDGE/ GATEWAY

WE0

BUFFER

68 100 pF 22 10K 10K 10K 1K TDI TDO TMS TRST WE TCK

Local Scan Port (LSP) Termination Strategy

Correct LSP termination is important to prevent erroneous sequencing of target scan chain devices. Correct TRST termination is important so that target devices are not asynchronously reset once control of the system access device is relinquished i.e. if devices are held in RTI whilst BIST is running the background. LSC buffering necessary if LSP’s cannot provide sufficient drive i.e. when IP core function is implemented within cPLD.

Presented By Stephen Harrison & Peter Collins ASIC

Slave Card B 3G ASIC

cPLD

Back-Plane Signals

Slot ID 1 TDI, TDO, TCK, TMS,TRST & WE Strobe

Back-Plane JTAG Signals

FPGA LSP3

LVDS

uP

BIST EEPROM

cPLD

ASIC Slave Card C

FPGA

cPLD

uP

cPLD

FPGA

LVDS

LSP3

Slot ID 2

JTAG Port JTAG Port JTAG Port

BIST EEPROM

MSC001

Scan Controller

STA101

Scan Controller

STA111

ScanBridge

MSC001

Scan Controller

STA101

Scan Controller

STA111

ScanBridge

ASIC

Slave Card A 3G ASIC

cPLD

FPGA LSP3

LVDS

uP

BIST EEPROM

cPLD MSC001

Scan Controller

STA101

Scan Controller

STA111

ScanBridge

Slot ID 0

Embedded Vector Delivery

Passive Backplane – Local Test Bus Master

Presented By Stephen Harrison & Peter Collins FPGA

System Master Card

FPGA

Back-Plane Signals

Slot ID 1 TDI, TDO, TCK, TMS,TRST & WE Strobe

Back-Plane JTAG Signals

EEPROM

uP

FPGA MSC001

Scan Controller

LSP 3 PCI Bridge

STA111

ScanBridge

STA101

Scan Controller

Slot ID 2

cPLD

uP Slave Card B

FPGA

cPLD

ASIC

cPLD

FPGA

LVDS

LSP3

STA111

ScanBridge

JTAG Port JTAG Port JTAG Port

Slot ID 0

Embedded Vector Delivery

Passive Backplane – System Test Bus Master

uP Slave Card A

FPGA

cPLD

ASIC

cPLD

FPGA

LVDS

LSP3

JTS03

Gateway

Presented By Stephen Harrison & Peter Collins Slot ID 1

TDI, TDO, TCK, TMS,TRST Back-Plane JTAG Signals

Slot ID 2

uP Slave Card B

FPGA

cPLD

ASIC

cPLD

FPGA

LVDS

LSP3

STA111

ScanBridge

JTAG Port JTAG Port

uP

EEPROM

STA101

Scan Controller

Active Back-Plane

uP Slave Card A

FPGA

cPLD

ASIC

cPLD

FPGA

LVDS

LSP3

JTS03

Gateway

Embedded Vector Delivery

Active Backplane - System Test Bus Master

Presented By Stephen Harrison & Peter Collins

Embedded Vector Delivery

Passive Backplane – BIST Sequencer

FPGA

System Master Card

FPGA ASIC

Slave Card A 3G ASIC

cPLD

Back-Plane Signals

Slot ID 1 TDI, TDO, TCK, TMS,TRST & WE Strobe

Back-Plane JTAG Signals

JTS02

BIST Sequencer

JTS03

Gateway

FPGA LSP3

LVDS

uP

BIST EEPROM

cPLD

EEPROM

uP

FPGA MSC001

Scan Controller

LSP 3 PCI Bridge

STA111

ScanBridge

STA101

Scan Controller

uP Slave Card B

FPGA

cPLD

ASIC

cPLD

FPGA

LVDS

LSP3

STA111

ScanBridge

Slot ID 2

cPLD

JTAG Port JTAG Port JTAG Port

Slot ID 0

Presented By Stephen Harrison & Peter Collins

BIST Sequences can be initiated by:- Power ON Reset Front Panel Reset Run BIST command

BIST Sequencer Overview

The BIST Sequencer (JTS02) provides :

The BIST Sequencer allows locally stored test vectors to be executed via the Bridge The resultant test signatures are compressed in the BIST Sequencer and compared against the expected signature Test result signatures are stored within local flash for access via the SPI/I2C interface

BIST Flash Memory

BIST Sequencer

JTS02 SPI Interface Power On & Push Button Resets

Gateway JTS03

LSP 1, 2 & 3 Primary Scan Port, A/W Pass thru & Slot address Board ID

BIST Status & Control

CPU

BIST Run Signal

BIST Data

BIST Set-up/Control Logic

Data

Presented By Stephen Harrison & Peter Collins

Interface Logic

Combination JTAG Bridge/G-way & BIST Sequencer

JTAG Port & Slot ID Primary Board I/O Memory

ASIC with ICBIST & JTAG XLI

LSC 1 LSC 1

FPGA

LSC 1

FPGA with ICBIST ASIC with ICBIST & JTAG XLI

LSC 1

ASIC with ICBIST, MemBIST-Xt & JTAG XLI

LSC 1 LSC 1 Memory BIST Flash

CPU

LSC 1 LSC 1 At Speed JTAG Interconnect Memory BIST-Xt Test Standard JTAG Interconnect LSC 2 & 3

Board & Device Level BIST Strategy

Presented By Stephen Harrison & Peter Collins

CONCLUSION

• It is important that board & system designers are

aware of the benefits and effectiveness of extending a 1149.1 test architecture for system level test and diagnosis.

• The architectural features discussed have been

readily adopted by leading silicon vendors so that system architects have more choice and flexibility for implementing a system test architecture.

• Leading 1149.1 tools vendors provide ATPG support.
• There is now a definite affinity with the Multidrop

solutions provided the Gateway, ScanBridge and Addressable Scan Port devices.

• There are limitations with robustness and fault

tolerance of the 1149.1 solutions, some of which were addressed by the 1149.5 MTM-Bus Standard.