Building Manycore Processor-to-DRAM Networks with Monolithic Silicon - - PowerPoint PPT Presentation

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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon - - PowerPoint PPT Presentation

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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics Christopher Batten 1 , Ajay Joshi 1 , Jason Orcutt 1 , Anatoly Khilo 1 Benjamin Moss 1 , Charles Holzwarth 1 , Milo c 1 , Hanqing Li 1 s Popovi Henry Smith 1 , Judy

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Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics

Christopher Batten1, Ajay Joshi1, Jason Orcutt1, Anatoly Khilo1 Benjamin Moss1, Charles Holzwarth1, Miloˇ s Popovi´ c1, Hanqing Li1 Henry Smith1, Judy Hoyt1, Franz K¨ artner1, Rajeev Ram1 Vladimir Stojanovi´ c1, Krste Asanovi´ c2

1 Department of Electrical Engineering and Computer Science

Massachusetts Institute of Technology, Cambridge, MA

2 Department of Electrical Engineering and Computer Science

University of California, Berkeley, CA Symposium on High Performance Interconnects August 27, 2008

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Motivation Photonic Technology Network Architecture Full System Design

The manycore memory bandwidth challenge

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Motivation Photonic Technology Network Architecture Full System Design

The manycore memory bandwidth challenge

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Motivation Photonic Technology Network Architecture Full System Design

Cost of electrical processor-to-DRAM networks

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Motivation Photonic Technology Network Architecture Full System Design

Cost of electrical processor-to-DRAM networks

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Motivation Photonic Technology Network Architecture Full System Design

Cost of electrical processor-to-DRAM networks

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Motivation Photonic Technology Network Architecture Full System Design

Cost of electrical processor-to-DRAM networks

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Motivation Photonic Technology Network Architecture Full System Design

Motivation Photonic Technology Network Architecture Full System Design

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

  • Light coupled into waveguide on chip A

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

  • Light coupled into waveguide on chip A
  • Transmitter off : Light extracted by ring modulator

MIT/UCB Christopher Batten 5 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

  • Light coupled into waveguide on chip A
  • Transmitter off : Light extracted by ring modulator
  • Transmitter on : Light passes by ring modulator

MIT/UCB Christopher Batten 5 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

  • Light coupled into waveguide on chip A
  • Transmitter off : Light extracted by ring modulator
  • Transmitter on : Light passes by ring modulator
  • Light continues to receiver on chip B

MIT/UCB Christopher Batten 5 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Seamless On-Chip/Off-Chip Photonic Link

  • Light coupled into waveguide on chip A
  • Transmitter off : Light extracted by ring modulator
  • Transmitter on : Light passes by ring modulator
  • Light continues to receiver on chip B
  • Light extracted by receiver’s ring filter

and guided to photodetector

MIT/UCB Christopher Batten 5 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Photonic Component Characterization

Standard CMOS process

  • Waveguides
  • Ring Modulators
  • Ring Filters
  • Photodetectors

Simulation 65 nm Test Chip

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Motivation Photonic Technology Network Architecture Full System Design

Photonic Component: Waveguide

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Motivation Photonic Technology Network Architecture Full System Design

Photonic Component: Ring Modulator

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Motivation Photonic Technology Network Architecture Full System Design

Photonic Component: Ring Filter

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Motivation Photonic Technology Network Architecture Full System Design

Photonic Component: Photodetector

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Motivation Photonic Technology Network Architecture Full System Design

Silicon photonic’s energy and area advantage

Bandwidth Energy Density (pJ/b) (Gb/s/µm) Global on-chip photonic link 0.25 160-320 Global on-chip optimally repeated M9 wire in 32 nm 1 5 Off-chip photonic link (50 µm coupler pitch) 0.25 13-26 Off-chip electrical SERDES (50 µm pitch) 5 0.2 On-chip/off-chip seamless photonic link 0.25

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Motivation Photonic Technology Network Architecture Full System Design

Motivation Photonic Technology Network Architecture Full System Design

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Motivation Photonic Technology Network Architecture Full System Design

Leveraging silicon photonics to address the memory bandwidth challenge

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Motivation Photonic Technology Network Architecture Full System Design

Baseline Network Architecture: Mesh Topology

Logical View Physical View

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Motivation Photonic Technology Network Architecture Full System Design

Analytical modeling of energy and throughput tradeoffs

20 40 60 80 100 120 2 4 6 8 Mesh Channel Bitwidth (b/cycle) Total Energy (nJ/cycle)

Mesh Channels Mesh Routers Off−chip I/O Channels

20 40 60 80 100 120 2 4 6 8 Mesh Channel Bitwidth (b/cycle) Total Ideal Throughput (Kb/cycle)

M e s h L i m i t e d I/O Limited (5 pJ/b)

  • 22 nm – 256 cores @ 2.5 GHz
  • Performance will most likely be

energy constrained

  • Fixed 8 nJ/cycle energy budget (20W)
  • Use simple gate-level models to

estimate energy, ideal throughput under uniform random traffic, and zero-load latency

MIT/UCB Christopher Batten 15 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Analytical modeling of energy and throughput tradeoffs

20 40 60 80 100 120 2 4 6 8 Mesh Channel Bitwidth (b/cycle) Total Energy (nJ/cycle)

Mesh Channels Mesh Routers Off−chip I/O Channels

20 40 60 80 100 120 2 4 6 8 Mesh Channel Bitwidth (b/cycle) Total Ideal Throughput (Kb/cycle)

M e s h L i m i t e d I/O Limited (5 pJ/b) I/O Limited (250 fJ/b)

  • 22 nm – 256 cores @ 2.5 GHz
  • Performance will most likely be

energy constrained

  • Fixed 8 nJ/cycle energy budget (20W)
  • Use simple gate-level models to

estimate energy, ideal throughput under uniform random traffic, and zero-load latency

MIT/UCB Christopher Batten 15 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Ideal throughput vs. off-chip I/O energy efficiency

1 2 3 4 5 2 4 6 8 photonic range electrical range Off−chip I/O Energy (pJ/b) Ideal Throughput (Kb/cycle) 1 2 3 4 5 75 125 175 225 photonic range electrical range Off−chip I/O Energy (pJ/b) Zero−Load Latency (cycles)

  • Decreased off-chip I/O energy,

results in more I/O bandwidth and mesh bandwidth

  • Latency decreases slightly due to

lower serialization latency

  • In photonic range almost all of the

energy is being spent on the mesh

  • A more energy efficient on-chip

interconnect should further improve throughput

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Motivation Photonic Technology Network Architecture Full System Design

Mesh Augmented with Global Crossbar

Logical View Physical View

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Motivation Photonic Technology Network Architecture Full System Design

Analytical modeling of global crossbar topology

1 2 3 4 5 10 20 30 Off−chip I/O Energy (pJ/b) Ideal Throughput (Kb/cycle)

Simple Mesh Mesh w/ 4 Groups Mesh w/ 16 Groups

1 2 3 4 5 75 125 175 225 photonic range electrical range Off−chip I/O Energy (pJ/b) Zero−Load Latency (cycles)

  • Global crossbar increases energy

efficiency of the on-chip interconnect improving throughput

  • Global traffic is moved from energy-

inefficient mesh channels to energy- efficient on-chip silicon photonics

  • Global crossbar has little impact in

the electrical range since very little energy is being spent in the on-chip interconnect to begin with

  • Latency decreases due to lower

serialization and hop latency

MIT/UCB Christopher Batten 18 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Simulation Methodology

  • Execution driven cycle-accurate network simulator
  • Models pipeline latencies, router contention,

credit-based flow control, and serialization overheads

  • Configuration same as in analytical modeling except:

– Mesh networks use dimension ordered routing – 16 DRAM modules distributed around chip – Memory channels cache-line interleaved – Normalized buffering in terms of bits

MIT/UCB Christopher Batten 19 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Simulation Results

2 4 6 8 10 100 200 300 400 500 Total Offered Bandwidth (Kb/cycle) Average Latency (cycles) Electrical System (5 pJ/b) 2 4 6 8 10 100 200 300 400 500 Total Offered Bandwidth (Kb/cycle) Average Latency (cycles) Photonic System (250 fJ/b)

  • Synthetic uniform random traffic

with 256 bit messages

  • For simple mesh (no groups) we see

a ≈2× improvement in throughput at similar latency

MIT/UCB Christopher Batten 20 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Simulation Results

2 4 6 8 10 100 200 300 400 500 Total Offered Bandwidth (Kb/cycle) Average Latency (cycles) Electrical System (5 pJ/b)

Simple Mesh Mesh w/ 4 Groups Mesh w/ 16 Groups

2 4 6 8 10 100 200 300 400 500 Total Offered Bandwidth (Kb/cycle) Average Latency (cycles) Photonic System (250 fJ/b)

  • Synthetic uniform random traffic

with 256 bit messages

  • For simple mesh (no groups) we see

a ≈2× improvement in throughput at similar latency

  • Adding global crossbar improves

performance of photonic system but has little impact on electrical system

  • Throughput is improved by ≈8-10×

and best throughput is ≈5 TB/s

MIT/UCB Christopher Batten 20 / 25

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Motivation Photonic Technology Network Architecture Full System Design

Motivation Photonic Technology Network Architecture Full System Design

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Motivation Photonic Technology Network Architecture Full System Design

Simplified 16-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Simplified 16-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Simplified 16-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Simplified 16-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Simplified 16-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Full 256-core system design

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Motivation Photonic Technology Network Architecture Full System Design

Advantages of photonics for packaging and system-level integration

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Motivation Photonic Technology Network Architecture Full System Design

Advantages of photonics for packaging and system-level integration

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Motivation Photonic Technology Network Architecture Full System Design

Take Away Points

  • Silicon photonics is a promising technology

for increasing the energy efficiency and the bandwidth density for on-chip and off-chip interconnect.

  • Addressing the manycore bandwidth

challenge requires implementing both global on-chip interconnect and off-chip I/O with photonics.

  • We can efficiently implement global all-to-all

connectivity with silicon photonics by using vertical waveguides, horizontal waveguides, and a ring filter matrix where they cross.

MIT/UCB Christopher Batten 25 / 25