Built- -In Self In Self- -Test for Programmable Test for - - PowerPoint PPT Presentation

3/22/2006 VLSI Design & Test Seminar Series

Built Built-

• In Self

In Self-

• Test for Programmable

Test for Programmable I/O Buffers in I/O Buffers in FPGAs FPGAs and and SoCs SoCs

Sudheer Vemula and Charles Stroud Sudheer Vemula and Charles Stroud

Electrical and Computer Engineering Electrical and Computer Engineering Auburn University Auburn University presented at 2006 IEEE Southeastern presented at 2006 IEEE Southeastern Symp

• Symp. On

. On System Theory System Theory

3/22/2006 VLSI Design & Test Seminar Series

Outline of Presentation Outline of Presentation

• Motivation and Background

Motivation and Background

• Overview of programmable I/O buffers

Overview of programmable I/O buffers

• Built

Built-

• In Self

In Self-

• Test Architecture

Test Architecture

• Results Retrieval and Diagnosis

Results Retrieval and Diagnosis

• Embedded Processor Based BIST

Embedded Processor Based BIST

• Experimental Results

Experimental Results

• Atmel AT94K series

Atmel AT94K series SoC SoC

• Xilinx Virtex

Xilinx Virtex-

• 4 series

4 series FPGAs FPGAs

• Summary

Summary

3/22/2006 VLSI Design & Test Seminar Series

Programmable I/O Buffers Programmable I/O Buffers

• Programmable I/O buffer can be:

Programmable I/O buffer can be:

• Input, Output, Bi

Input, Output, Bi-

• directional

directional

• Package connections

Package connections

• Bonded or

Bonded or unbonded unbonded

• Different types (some FPGAs)

Different types (some FPGAs)

• Primary, Secondary, Clock

Primary, Secondary, Clock

• Programmable resources

Programmable resources

• Logic

Logic

• Multiplexers, flip

Multiplexers, flip-

• flops, latches

flops, latches

• Virtex

Virtex-

• 4: 32

4: 32 MUXs MUXs & 10 & 10 FFs FFs

• Active levels

Active levels

• Enables, set/reset, clocks

Enables, set/reset, clocks

• Pull

Pull-

• up, pull

up, pull-

• down, keeper

down, keeper

• Drive capabilities

Drive capabilities

• Delays, slew rate

Delays, slew rate

• I/O voltage standards (Virtex

I/O voltage standards (Virtex-

• 4: 69)

4: 69)

• Routing resources to/from

Routing resources to/from FPGA core FPGA core

CLB CLB CLB CLB I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O

= primary I/O = primary I/O buffer buffer = secondary I/O = secondary I/O buffer buffer

X X X X X X X X X X X X X X X X Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y

Boundary Boundary Scan Scan Access Access

Tri Tri-

• state Control

state Control Output Data Output Data Input Data Input Data PAD PAD

to/from internal to/from internal programmable programmable routing resources routing resources

3/22/2006 VLSI Design & Test Seminar Series

Motivation and Background Motivation and Background

• Need to test programmable I/O buffers in

Need to test programmable I/O buffers in FPGAs FPGAs to insure proper system operation to insure proper system operation

• Boundary Scan lacks access to all resources

Boundary Scan lacks access to all resources in programmable I/O buffers in programmable I/O buffers

• Configurable

Configurable SoCs SoCs often incorporate

• ften incorporate

programmable I/O buffers for FPGA cores programmable I/O buffers for FPGA cores

• FPGA synthesis tools often use resources

FPGA synthesis tools often use resources in in unbonded unbonded I/O buffers for system function I/O buffers for system function

• Prior work in Built

Prior work in Built-

• In Self

In Self-

• Test for

Test for FPGAs FPGAs

• BIST for internal logic and routing resources

BIST for internal logic and routing resources

• No BIST for programmable I/O buffers

No BIST for programmable I/O buffers

3/22/2006 VLSI Design & Test Seminar Series

Increase in Resources in I/O Buffers Increase in Resources in I/O Buffers

804 (XCV3200E) 804 (XCV3200E)

2002 2002 3 3

XILINX VIRTEX E XILINX VIRTEX E 1164 1164 (XC2VP70/100/ (XC2VP70/100/ XC2VPX70) XC2VPX70)

2003 2003 6 6

XILINX XILINX VIRTEX II PRO VIRTEX II PRO 512 (XCV1000) 512 (XCV1000)

2002 2002 3 3

XILINX XILINX VIRTEX VIRTEX 960 960 (XC4VLX200) (XC4VLX200) 784 784 (XC3S5000) (XC3S5000) 256 (AT94S40) 256 (AT94S40) 384 (AT40K40) 384 (AT40K40)

• Max. No. of I/O
• Max. No. of I/O

Buffers Buffers

2005 2005 10 10

XILINX VIRTEX 4 XILINX VIRTEX 4

2005 2005 6 6

XILINX XILINX SPARTAN3 SPARTAN3

2002 2002 2 2

ATMEL ATMEL AT94K AT94K

1999 1999

ATMEL ATMEL AT40(10)K AT40(10)K

Year Year

• No. of
• No. of

Registers per Registers per I/O Buffer I/O Buffer

FPGA/Soc FPGA/Soc

3/22/2006 VLSI Design & Test Seminar Series

I/O Buffer BIST Architecture I/O Buffer BIST Architecture

• Configure bi

Configure bi-

• directional buffer under test (BUT)

directional buffer under test (BUT)

• Output response analyzer (ORA) comparison

Output response analyzer (ORA) comparison-

• based

based

• Latches mismatches due to faults in BUT

Latches mismatches due to faults in BUT

• Output of BUT compared by 2

Output of BUT compared by 2 ORAs ORAs with 2 other with 2 other BUTs BUTs

• Test pattern generator (TPG) = counter or LFSR

Test pattern generator (TPG) = counter or LFSR

• Implemented in FPGA Configurable Logic Blocks (

Implemented in FPGA Configurable Logic Blocks (CLBs CLBs) )

• Multiple

Multiple TPGs TPGs prevent prevent CLBs CLBs faults from masking IOB faults from masking IOB faults faults

=TPG =ORA

3/22/2006 VLSI Design & Test Seminar Series

Programmable Programmable Routing Resources Routing Resources from TPG to ORA

• Test patterns applied to all possible inputs to I/O

Test patterns applied to all possible inputs to I/O buffers to test routing resources buffers to test routing resources

• Multiple BIST configurations needed to completely

Multiple BIST configurations needed to completely test I/O buffer in all modes of operation test I/O buffer in all modes of operation

I/O Buffer BIST Architecture I/O Buffer BIST Architecture

3/22/2006 VLSI Design & Test Seminar Series

ORA Designs ORA Designs

• Comparator

Comparator-

• based design

based design

• feedback & flip

feedback & flip-

• flop latch any

flop latch any mismatch due to faults in Buffers mismatch due to faults in Buffers Under Test ( Under Test (BUTs BUTs) )

• ORA results retrieval

ORA results retrieval

• Integrated ORA and scan chain

Integrated ORA and scan chain

• More logic for scan chain

More logic for scan chain

• Interface to Boundary Scan

Interface to Boundary Scan

• Configuration memory

Configuration memory readback readback

• No added logic for scan chain

No added logic for scan chain

• Partial configuration memory

Partial configuration memory readback readback

• Readback

Readback from embedded processor from embedded processor

• Diagnosis performed by embedded

Diagnosis performed by embedded processor processor Outputs from BUTs LUT Outputs From BUTs LUT Shift In Shift LUT

3/22/2006 VLSI Design & Test Seminar Series

Circular Comparison Diagnosis Circular Comparison Diagnosis

Step 1: Step 1: Record ORA results Record ORA results Step 2: Step 2: Mark all Buffers Under Test ( Mark all Buffers Under Test (BUTs BUTs) associated with ) associated with two or more consecutive ORAs with 0s (0=fault two or more consecutive ORAs with 0s (0=fault-

• free)

free) Step 3: Step 3: Recursively mark Recursively mark BUTs BUTs with 1 (1=faulty) for every with 1 (1=faulty) for every consecutive 0 and 1 followed by empty cell consecutive 0 and 1 followed by empty cell Step 4: Step 4: Inconsistencies mean fault in BUT Inconsistencies mean fault in BUT-

• to

to-

• ORA routing

ORA routing resources or in resources or in ORAs ORAs if they have not been tested and if they have not been tested and known to be fault known to be fault-

• free

free Step 5: Step 5: Unique diagnosis if all Unique diagnosis if all BUTs BUTs marked faulty or fault marked faulty or fault-

• free

free Note: buffers B3 and B4 have equivalent faults Note: buffers B3 and B4 have equivalent faults

B9 B8 1 O89 O67 B7 1 O78 B6 B5 O56 O91 O12 B2 1 O23 B3 O34 1 O45 B4 B1 O91 B9 B8 1 O89 O67 B7 1 O78 B6 B5 O56 O91 O12 B2 1 O23 B3 O34 1 O45 B4 B1 O91 B9 1 B8 1 O89 O67 B7 1 O78 B6 B5 O56 O91 O12 B2 1 O23 1 B3 O34 1 1 O45 B4 B1 O91

3/22/2006 VLSI Design & Test Seminar Series

Embedded Processor Based BIST Embedded Processor Based BIST

• Given access to FPGA configuration

Given access to FPGA configuration memory, an embedded processor can memory, an embedded processor can

• Reconfigure I/O buffers in various modes of

Reconfigure I/O buffers in various modes of

• peration
• peration
• Execute BIST sequence

Execute BIST sequence

• Retrieve BIST results from

Retrieve BIST results from ORAs ORAs

• Perform diagnosis based on BIST results

Perform diagnosis based on BIST results

• Processor can be hard or soft core

Processor can be hard or soft core

• Significant improvements in

Significant improvements in

• Memory for storing BIST configurations

Memory for storing BIST configurations

• Test time

Test time

3/22/2006 VLSI Design & Test Seminar Series

Atmel AT94K Implementation Atmel AT94K Implementation

• Three sets of BIST configurations

Three sets of BIST configurations

• primary I/O buffers

primary I/O buffers

• 13 configurations total

13 configurations total

• secondary I/O buffers

secondary I/O buffers

• 10 configurations total

10 configurations total

• global reset in primary & secondary

global reset in primary & secondary

• ≈

≈ 2x3 2x3N N configurations total configurations total

• where

where N N = # = #CLBs CLBs in one dimension in one dimension

• N=24 for AT94K10, N=48 for AT94K40 (280 I/O buffers)

N=24 for AT94K10, N=48 for AT94K40 (280 I/O buffers)

• Subsequent BIST configurations via dynamic

Subsequent BIST configurations via dynamic partial reconfiguration from AVR processor core partial reconfiguration from AVR processor core

• Reduces test time compared to download for 303 BIST

Reduces test time compared to download for 303 BIST configs configs

• Compared to 68

Compared to 68 configs configs for FPGA core for FPGA core

A V R I/O I/O Buffers Buffers ORA ORA Comparison Comparison Loops Loops

3/22/2006 VLSI Design & Test Seminar Series

Fault Detection in Atmel AT94K Fault Detection in Atmel AT94K

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 1 2 3 4 5 6 7 8 9 10 11 12 13

BIST Configurations Fault Coverage (FC)

Primary I/O buffer Primary I/O buffer Secondary I/O buffer Secondary I/O buffer Additional global reset BIST configuration obtains Additional global reset BIST configuration obtains 100% fault coverage (including routing resources) 100% fault coverage (including routing resources)

3/22/2006 VLSI Design & Test Seminar Series

Architecture of the Virtex Architecture of the Virtex-

• 4 I/O Buffer

4 I/O Buffer

ILGOIC (Input to FPGA) OLOGIC (Ouptut from FPGA) PAD_LOGIC

Main Components of an I/O Buffer

3/22/2006 VLSI Design & Test Seminar Series

OLOGIC Block:-

• Sources output to pad

Sources output to pad

• 6 storage elements

6 storage elements

• 3 for tri

3 for tri-

• state control

state control

• 3 for output data

3 for output data

• Both sets of registers

Both sets of registers have same functionality have same functionality

• Only upper register can

Only upper register can be configured as either be configured as either Flip Flip-

• Flop or latch

Flop or latch

This is a sequential circuit when operated in DDR mode

D SR REV D SR REV D SR REV D OCE SR REV D SR REV D SR REV

CLK CLK1 CLK2

TDDRA TDDRB ODDRB ODDRA

D1 D2 T2 T1

OCE OCE TCE TCE TCE

CLK CLK CLK CLK

T

3/22/2006 VLSI Design & Test Seminar Series

ILOGIC Block: ILOGIC Block:-

• Gets input from the pad

Gets input from the pad

• Consists of

Consists of

• 64 tap delay element

64 tap delay element (variable or fixed) (variable or fixed)

• Flip

Flip-

• Flops (registered

Flops (registered

• utputs and Double Data
• utputs and Double Data

Rate (DDR) registers) Rate (DDR) registers)

• 3 different outputs

3 different outputs

• Unregistered direct connection

Unregistered direct connection

• Different modes of operation of

Different modes of operation of DDR registers DDR registers

• Only upper register can be

Only upper register can be configured as either Flip configured as either Flip-

• Flop or latch

Flop or latch

3/22/2006 VLSI Design & Test Seminar Series

Tri-state control

Pad Logic:-

• Virtex

Virtex-

• 4 buffers

4 buffers

• 69 I/O standards

69 I/O standards

• Only 5 can be used in bi

Only 5 can be used in bi-

• directional mode

directional mode

• 7 drive capabilities

7 drive capabilities

• All can be tested in bi

All can be tested in bi-

• di

di mode mode

• 2 slew rate options

2 slew rate options

• All can be tested in bi

All can be tested in bi-

• di

di mode mode

• Pull

Pull-

• up, Pull

up, Pull-

• down and Keeper circuits

down and Keeper circuits

• All can be tested in bi

All can be tested in bi-

• di

di mode mode

3/22/2006 VLSI Design & Test Seminar Series

Proposed Virtex Proposed Virtex-

• 4 Implementation

4 Implementation

• Circular comparison architecture

Circular comparison architecture

• Multiple

Multiple TPGs TPGs to prevent fault masking to prevent fault masking

• All programmable I/O buffers are identical

All programmable I/O buffers are identical

• 32 multiplexers plus 10 flip

32 multiplexers plus 10 flip-

• flops per I/O buffer

flops per I/O buffer

• # I/O buffers

# I/O buffers

• 320 for LX15, SX25, FX12, FX20 (smallest devices)

320 for LX15, SX25, FX12, FX20 (smallest devices)

• 960 for LX100, LX160, LX200 (largest devices)

960 for LX100, LX160, LX200 (largest devices)

• All can be tested concurrently

All can be tested concurrently

• Only one set of BIST configurations

Only one set of BIST configurations

• Seven BIST configurations total

Seven BIST configurations total

• Tests only bi

Tests only bi-

• directional I/O voltage standards

directional I/O voltage standards

• Does not test all routing resources associated with I/O

Does not test all routing resources associated with I/O buffers buffers

3/22/2006 VLSI Design & Test Seminar Series

Fault Detection in Virtex Fault Detection in Virtex-

• 4

4

• Can only test bi

Can only test bi-

• directional buffer modes

directional buffer modes

• Undetectable faults due to bi

Undetectable faults due to bi-

• directional mode

directional mode

50 100 150 200 250 300 350 400 450 500 550 1 2 3 4 5 6 7

BIST Configuration # # Faults Detected

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%

% Fault Coverage

Individual FC Cumulative FC

• Embedded

Embedded processor processor cores cores

• PowerPC

PowerPC

• hard core

hard core

• MicroBlaze

MicroBlaze

• soft core

soft core

3/22/2006 VLSI Design & Test Seminar Series

Capabilities and Limitations Capabilities and Limitations

• Can detect all catastrophic faults in routing,

Can detect all catastrophic faults in routing, logic, and configuration memory bits logic, and configuration memory bits

• Cannot detect some parametric faults

Cannot detect some parametric faults

• V

VIL

IL, V

, VIH

IH, V

, VOL

OL, V

, VOH

OH, delay, drive capabilities, etc.

, delay, drive capabilities, etc.

• Can be used for manufacturing testing

Can be used for manufacturing testing

• Package independent test

Package independent test

• May not always be usable for system level

May not always be usable for system level testing without some failures testing without some failures

• Must be able to tri

Must be able to tri-

• state all outputs of other

state all outputs of other devices on PCB devices on PCB

• Sensitive to system component connections

Sensitive to system component connections

• Example: LED bias current

Example: LED bias current

3/22/2006 VLSI Design & Test Seminar Series

Summary Summary

• Previous BIST approaches for

Previous BIST approaches for FPGAs FPGAs

• Programmable logic and routing in core of FPGA

Programmable logic and routing in core of FPGA

• No previous BIST for programmable I/O buffers

No previous BIST for programmable I/O buffers

• Unbonded

Unbonded I/O frequently used by synthesis tools for I/O frequently used by synthesis tools for additional logic/routing additional logic/routing

• BIST approach for I/O buffers

BIST approach for I/O buffers

• Circular comparison based approach

Circular comparison based approach

• Good fault detection capabilities and diagnostic resolution

Good fault detection capabilities and diagnostic resolution

• Embedded processor (hard or soft) reduces test time

Embedded processor (hard or soft) reduces test time

• Dynamic partial reconfiguration

Dynamic partial reconfiguration

• BIST execution, results retrieval and diagnosis

BIST execution, results retrieval and diagnosis

• Can detect catastrophic faults in logic and routing

Can detect catastrophic faults in logic and routing

• But cannot detect all parametric faults

But cannot detect all parametric faults

3/22/2006 VLSI Design & Test Seminar Series

System System-

• Level BIST for

Level BIST for Programmable I/O Buffers in Programmable I/O Buffers in FPGAs FPGAs and and SoCs SoCs

Lee Lerner, Sudheer Vemula and Charles Stroud Lee Lerner, Sudheer Vemula and Charles Stroud

Electrical and Computer Engineering Electrical and Computer Engineering Auburn University Auburn University may be presented at 2006 IEEE North Atlantic Test Workshop may be presented at 2006 IEEE North Atlantic Test Workshop

3/22/2006 VLSI Design & Test Seminar Series

Outline Outline

• System Level BIST

System Level BIST

• Back driving problem

Back driving problem

• BIST Generation

BIST Generation

• VHDL approach

VHDL approach

• MGL or XDL approach

MGL or XDL approach

• Reconfiguration from embedded

Reconfiguration from embedded processor processor

• Summary

Summary

3/22/2006 VLSI Design & Test Seminar Series

System Level Implementation System Level Implementation

• Testing FPGA/

Testing FPGA/SoC SoC which is already placed on the PCB which is already placed on the PCB

• The FPGA/

The FPGA/SoC SoC will have input and output connections will have input and output connections

3/22/2006 VLSI Design & Test Seminar Series

Back Driving Problem Back Driving Problem

• Problems due to back drive

Problems due to back drive

• Signals from other devices on the PCB may

Signals from other devices on the PCB may cause BIST failure indications cause BIST failure indications

• Even when tri

Even when tri-

• stated

stated

• FPGA may be damaged due to high current

FPGA may be damaged due to high current

FPGA under test Chip 1 Output Buffer Bi-directional Buffer ‘1’ ‘1’ ‘0’

3/22/2006 VLSI Design & Test Seminar Series

BIST Generation BIST Generation

• VHDL Approach:

VHDL Approach:-

• Limited to supported VHDL macros

Limited to supported VHDL macros

• Develop a parameterized VHDL

Develop a parameterized VHDL

• Cannot test

Cannot test unbonded unbonded I/O Buffers I/O Buffers

• Cannot route to unconnected signals

Cannot route to unconnected signals

• Less Fault Coverage

Less Fault Coverage

• Parameterized VHDL can be developed easily

Parameterized VHDL can be developed easily

• Can be applied for any FPGA

Can be applied for any FPGA

• Still better than Boundary Scan

Still better than Boundary Scan

• The I/O Buffers placed using constraints file

The I/O Buffers placed using constraints file

• Can be easily done by user

Can be easily done by user

• Uses normal design flow

Uses normal design flow

3/22/2006 VLSI Design & Test Seminar Series

BIST Generation BIST Generation

• MGL or XDL Approach (High Effort):

MGL or XDL Approach (High Effort):-

• MGL

MGL – – Atmel Atmel’ ’s s Macro Generation Language Macro Generation Language

• XDL

XDL – – Xilinx Design Language Xilinx Design Language

• Parameterized program for MGL or XDL

Parameterized program for MGL or XDL

• Can test

Can test unbonded unbonded I/O Buffers I/O Buffers

• Can route to unconnected signals

Can route to unconnected signals

• Higher Fault Coverage

Higher Fault Coverage

• Better control over the resources

Better control over the resources

• Most resources can be tested

Most resources can be tested

• More difficult development than VHDL approach

More difficult development than VHDL approach

• Cannot be applied for any FPGA (other vendors)

Cannot be applied for any FPGA (other vendors)

• I/O Buffers placed by parameterized program

I/O Buffers placed by parameterized program

• Does not use normal design flow

Does not use normal design flow

3/22/2006 VLSI Design & Test Seminar Series

Embedded Processor Reconfiguration Embedded Processor Reconfiguration

• Atmel

Atmel

• Configuration memory is Byte addressable

Configuration memory is Byte addressable

• Configuration memory

Configuration memory readback readback is not present is not present

• Can

Can’ ’t test logic if logic bits are mixed with routing bits t test logic if logic bits are mixed with routing bits

• Lower fault coverage

Lower fault coverage

• Xilinx

Xilinx

• Configuration memory is Frame addressable

Configuration memory is Frame addressable

• No. of 32
• No. of 32-
• bit words per frame = 1312 (

bit words per frame = 1312 (Virtex Virtex 4) 4)

• Longer partial reconfiguration time

Longer partial reconfiguration time

• Configuration memory

Configuration memory readback readback is present is present

• Read

Read-

• Modify

Modify-

• Write operations to configuration memory

Write operations to configuration memory

• Logic can be tested independent of routing

Logic can be tested independent of routing

• Higher fault coverage

Higher fault coverage

3/22/2006 VLSI Design & Test Seminar Series

Write Write-

• only Reconfiguration Problem
• nly Reconfiguration Problem
• Initial Configuration: Q=

Initial Configuration: Q=‘ ‘1 1’ ’, B= , B=‘ ‘1 1’ ’

• Second Configuration: Q=

Second Configuration: Q=‘ ‘0 0’ ’, FF= , FF=‘ ‘1 1’ ’

• Can

Can’ ’t be written without knowing the multiplexer t be written without knowing the multiplexer select line (A,B,C,D or E) select line (A,B,C,D or E)

• With configuration memory read back, selected bits

With configuration memory read back, selected bits can be modified can be modified

3/22/2006 VLSI Design & Test Seminar Series

VHDL Experimental Results VHDL Experimental Results

• Atmel

Atmel -

• using existing BIBUF VHDL macro

using existing BIBUF VHDL macro

• Portable between AT40K series FPGA and

Portable between AT40K series FPGA and AT94K series AT94K series SoC SoC

• Can only test about 25% of resources

Can only test about 25% of resources

• Xilinx

Xilinx – – using existing IOBUF VHDL macro using existing IOBUF VHDL macro

• Portable between all

Portable between all Xilinx Xilinx FPGAs FPGAs

• Resources that can be tested varies with

Resources that can be tested varies with FPGA family and synthesis tools FPGA family and synthesis tools

• Limited control of resources under test

Limited control of resources under test

• Flip

Flip-

• flops not always synthesized into I/O buffers

flops not always synthesized into I/O buffers

3/22/2006 VLSI Design & Test Seminar Series

System System-

• Level BIST Summary

Level BIST Summary

• Two approaches

Two approaches

• VHDL

VHDL

• Limited by macro support

Limited by macro support

• MGL/XDL

MGL/XDL

• Boundary Scan

Boundary Scan comparison comparison

• Higher fault coverage

Higher fault coverage

• Unless FPGA supports

Unless FPGA supports INTEST INTEST

• Shorter test time & lower

Shorter test time & lower memory storage memory storage

• Further reductions with

Further reductions with partial reconfiguration via partial reconfiguration via embedded processor embedded processor

high high low low Development Development * * * * I/O Voltages I/O Voltages high high low low Fault coverage Fault coverage no no yes yes Portability Portability yes yes no no Non Non-

• bonded

bonded yes yes yes yes Pull Pull-

• up/down

up/down * * * * Drive/slew Drive/slew yes yes no no Routing Routing yes yes some some Logic Logic MGL/ MGL/ XDL XDL VHDL VHDL Test Test * * Can detect catastrophic faults Can detect catastrophic faults but not all parametric faults but not all parametric faults