CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN R.M. Dansereau; v.1.0 - - PowerPoint PPT Presentation

▶
chapter ii switch networks and switch design
SMART_READER_LITE
LIVE PREVIEW

CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN R.M. Dansereau; v.1.0 - - PowerPoint PPT Presentation

Nov 18, 2022 97 likes •353 views

SWITCH DESIGN CHAPTER II CHAPTER II-1 SWITCH DESIGN CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN R.M. Dansereau; v.1.0 SWITCH NETWORKS SWITCH DESIGN SWITCH NETWORKS CHAPTER II-2 BASIC IDEAL SWITCH SWITCH DESIGN Simplest

slide-1
SLIDE 1

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-1 SWITCH DESIGN

  • CHAPTER II

CHAPTER II SWITCH NETWORKS AND SWITCH DESIGN

slide-2
SLIDE 2

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-2

SWITCH NETWORKS

BASIC IDEAL SWITCH

SWITCH DESIGN

  • SWITCH NETWORKS
  • Simplest structure in a computing system is a switch
  • Path exists between INPUT and OUTPUT if Switch is CLOSED or ON
  • Path does not exist between INPUT and OUTPUT if SWITCH

is OPEN or OFF IDEAL SWITCH INPUT OUTPUT

slide-3
SLIDE 3

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-3

SWITCH NETWORKS

SWITCHES IN SERIES

SWITCH DESIGN

  • SWITCH NETWORKS
  • BASIC SWITCH

INPUT OUTPUT S1 S2

  • AND configuration

S1 S2 OFF OFF OFF ON ON ON OFF ON PATH? NO NO NO YES Truth Table SWITCHES IN SERIES

slide-4
SLIDE 4

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-4

SWITCH NETWORKS

SWITCHES IN PARALLEL

SWITCH DESIGN

  • SWITCH NETWORKS
  • BASIC SWITCH
  • SWITCHES IN SERIES

S1 S2 INPUT OUTPUT SWITCHES IN PARALLEL

  • OR configuration

S1 S2 OFF OFF OFF ON ON ON OFF ON PATH? NO YES YES YES Truth Table

slide-5
SLIDE 5

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-5

SWITCH NETWORKS

INPUT SELECTOR

SWITCH DESIGN

  • SWITCH NETWORKS
  • BASIC SWITCH
  • SWITCHES IN SERIES
  • SWITCHES IN PARALLEL

INPUT 1 INPUT 2 S1 S2 OUTPUT S1 S2 OFF OFF OFF ON ON ON OFF ON OUTPUT NONE INPUT 2 INPUT 1 UNKNOWN Truth Table

  • Crowbarred level where logic level is
  • indeterminate. Likely avoid this case.
slide-6
SLIDE 6

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-6

CMOS

CMOS SWITCHES

SWITCH DESIGN

  • SWITCH NETWORKS
  • SWITCHES IN SERIES
  • SWITCHES IN PARALLEL
  • INPUT SELECTOR
  • The idea is to use the series and parallel switch configurations to route

signals in a desired fashion.

  • Unfortunately, it is difficult to implement an ideal switch as given.
  • Complementary Metal Oxide Semiconductor (CMOS) devices give us

some interesting components. nMOS transistor pMOS transistor GATE SOURCE DRAIN GATE DRAIN SOURCE SWITCH INPUT OUTPUT IDEAL SWITCH

slide-7
SLIDE 7

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-7

CMOS

TRANSFER CHARACTERISTICS

SWITCH DESIGN

  • SWITCH NETWORKS
  • CMOS
  • CMOS SWITCHES

nMOS pMOS

  • nMOS when CLOSED
  • Transmits logic level 0 well
  • Transmits logic level 1 poorly
  • pMOS when CLOSED
  • Transmits logic level 1 well
  • Transmits logic level 0 poorly

S S S 1 SWITCH OPEN CLOSED S 1 SWITCH CLOSED OPEN

slide-8
SLIDE 8

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-8

CMOS

TRANSMISSION GATE (1)

SWITCH DESIGN

  • SWITCH NETWORKS
  • CMOS
  • CMOS SWITCHES
  • TRANSFER CHAR.

IDEAL SWITCH INPUT OUTPUT CMOS TRANSMISSION GATE INPUT OUTPUT (SWITCH) S S S S OUTPUT 1 Z INPUT nMOS pMOS OFF ON OFF ON INPUT OUTPUT S S

slide-9
SLIDE 9

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-9

CMOS

TRANSMISSION GATE (2)

SWITCH DESIGN

  • CMOS
  • CMOS SWITCHES
  • TRANSFER CHAR.
  • TRANSMISSION GATE

1 1 S = 1 S = 0 S = 1 S = 0 SPLIT OF CURRENT ACROSS A TRANSMISSION GATE LOGIC-0 AT INPUT LOGIC-1 AT INPUT FOR LOGIC-0 AND LOGIC-1 INPUT

slide-10
SLIDE 10

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-10

SWITCH NETWORKS

HIGH IMPEDANCE Z (1)

SWITCH DESIGN

  • CMOS
  • CMOS SWITCHES
  • TRANSFER CHAR.
  • TRANSMISSION GATE
  • With switches, we can consider three states for an output:
  • Logic-0
  • Logic-1
  • High Impedance Z
  • Path exists for Logic-0 and Logic-1 when the switch is CLOSED.
  • High impedance is a state where the switch is OPEN.

0/1 OUTPUT = 0/1 S 0/1 OUTPUT = Z S

slide-11
SLIDE 11

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-11

SWITCH NETWORKS

HIGH IMPEDANCE Z (2)

SWITCH DESIGN

  • CMOS
  • SWITCH NETWORKS
  • HIGH IMPEDANCE Z
  • Another way of thinking of switches is as follows
  • Path exists for Logic-0 and Logic-1 when the switch is CLOSED,

meaning that the impedance/resistance is small enough to allow amply flow of current.

  • High impedance is a state where the switch is OPEN, meaning that the

impedance/resistance is very large allowing nearly no current flow. 1 = CLOSED DRAIN SOURCE DRAIN SOURCE

10K « Ω

0 = OPEN DRAIN SOURCE DRAIN SOURCE

100M » Ω

slide-12
SLIDE 12

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-12

SWITCH NETWORKS

INVERTER (NOT)

SWITCH DESIGN

  • CMOS
  • SWITCH NETWORKS
  • HIGH IMPEDANCE Z

VDD A B A B 1 1 Z

  • This network inverts the binary input value. N

B A =

A B 1 1 A B 1 Z PULL-DOWN PULL-UP

The pull-up network should be ON whenever the

  • utput should be "1". It should be "Z" (OFF)

whenever the output should be "0". The pull-down network should be Z "OFF" whenever the output should be "1". It should be ON whenever the

  • utput should be "0". Here

"ON" implies "0" = Logic "1" = Logic "0"

slide-13
SLIDE 13

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-13

SWITCH NETWORKS

NAND NETWORK

SWITCH DESIGN

  • CMOS
  • SWITCH NETWORKS
  • HIGH IMPEDANCE Z
  • INVERTER

VDD A B C A B C 1 1 1 1 Z Z Z

C AB =

A B C 1 1 1 1 1 1 1 Z A B C 1 1 1 1 1 1 1 PULL-DOWN PULL-UP

The "o" on the gate means that "Logic 0" voltage turns the (P-type) transistor "ON". When the gate voltage is "Logic 1", the N-type transistor turns ON (no inversion).

slide-14
SLIDE 14

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-14

SWITCH NETWORKS

NOR NETWORK

SWITCH DESIGN

  • SWITCH NETWORKS
  • HIGH IMPEDANCE Z
  • INVERTER
  • NAND NETWORK

VDD B A C A B C 1 1 1 1 1 Z Z Z

C A B + =

A B C 1 1 1 1 Z A B C 1 1 1 1 1 PULL-DOWN PULL-UP

slide-15
SLIDE 15

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-15

SWITCH NETWORKS

AND NETWORK

SWITCH DESIGN

  • SWITCH NETWORKS
  • INVERTER
  • NAND NETWORK
  • NOR NETWORK

A B C 1 1 1 1 1

C AB =

VDD C VDD A B NAND INVERTER

slide-16
SLIDE 16

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-16

SWITCH NETWORKS

OR NETWORK

SWITCH DESIGN

  • SWITCH NETWORKS
  • NAND NETWORK
  • NOR NETWORK
  • AND NETWORK

VDD C NOR INVERTER VDD B A A B C 1 1 1 1 1 1 1

C A B + =

slide-17
SLIDE 17

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-17

SWITCH NETWORKS

XOR NETWORK

SWITCH DESIGN

  • SWITCH NETWORKS
  • NOR NETWORK
  • AND NETWORK
  • OR NETWORK

A B C 1 1 1 1 1 1

C AB AB + =

A B A B A B A B VDD C

slide-18
SLIDE 18

_ B-- _ A-- Complementary Circuits Boolean Equality AB+A’B’ = (A+B’)(A’+B) Because AA’ = BB’ = 0

slide-19
SLIDE 19

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-18

SWITCH NETWORKS

XNOR NETWORK

SWITCH DESIGN

  • SWITCH NETWORKS
  • AND NETWORK
  • OR NETWORK
  • XOR NETWORK

A B C 1 1 1 1 1 1

C AB AB + =

A B A B A B A B VDD VDD C

  • Can this be implemented without the extra

inverter at the output? Answer: Y es!

slide-20
SLIDE 20

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-19

SWITCH NETWORKS

PULL-UP/PULL-DOWN

SWITCH DESIGN

  • SWITCH NETWORKS
  • OR NETWORK
  • XOR NETWORK
  • XNOR NETWORK

A B C 1 1 1 1

D AC B + =

D Z Z 1 1 1 1 1 1 1 1 Z Z Z C B A C A B VDD D A B C 1 1 1 1 D Z Z 1 1 1 1 1 1 1 1 1 1 1 Z 1 1 PULL-UP PULL-DOWN

slide-21
SLIDE 21

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-20

SWITCH NETWORKS

FUNCTION IMPLEMENTATION

SWITCH DESIGN

  • SWITCH NETWORKS
  • XOR NETWORK
  • XNOR NETWORK
  • PULL-UP/PULL-DOWN
  • Most Boolean functions can be easily implemented using switches.
  • The basic rules are as follows
  • Pull-up section of switch network
  • Use complements for all literals in expression
  • Use only pMOS devices
  • Form series network for an AND operation
  • Form parallel network for an OR operation
  • Pull-down section of switch network
  • Use complements for all literals in expression
  • Use only nMOS devices
  • Form parallel network for an AND operation
  • Form series network for an OR operation
slide-22
SLIDE 22

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-21

SWITCH NETWORKS

EXAMPLE PULL-UP

SWITCH DESIGN

  • SWITCH NETWORKS
  • XNOR NETWORK
  • PULL-UP/PULL-DOWN
  • FUNC. IMPLEMENTATION
  • To implement the Boolean function given below, the following pull-up

network could be designed.

F

A

D

A

C B E

VDD

F E AD B A C + ( ) + ( ) =

slide-23
SLIDE 23

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-22

SWITCH NETWORKS

EXAMPLE PULL-DOWN

SWITCH DESIGN

  • SWITCH NETWORKS
  • PULL-UP/PULL-DOWN
  • FUNC. IMPLEMENTATION
  • EXAMPLE PULL-UP
  • To complete the switch design, the pull-down section for the Boolean

function must also be designed.

  • Notice how AND and OR become OR and AND circuits, respectively.

A C B A D E

F

F E AD B A C + ( ) + ( ) =

slide-24
SLIDE 24

R.M. Dansereau; v.1.0

SWITCH DESIGN CHAPTER II-23

SWITCH NETWORKS

COMPLETED EXAMPLE

SWITCH DESIGN

  • SWITCH NETWORKS
  • FUNC. IMPLEMENTATION
  • EXAMPLE PULL-UP
  • EXAMPLE PULL-DOWN
  • Putting the pull-up and pull-down pieces together gives the following

CMOS switch implementation of the Boolean function.

A C B A D E A

D

A

C B E

VDD

PULL-UP PULL-DOWN

F E AD B A C + ( ) + ( ) =