Cognitive Radio Platform Technology Ivan Seskar WINLAB Rutgers, - PowerPoint PPT Presentation

Cognitive Radio Platform Technology Ivan Seskar WINLAB Rutgers, The State University of New Jersey www.winlab.rutgers.edu seskar (at) winlab (dot) rutgers (dot) edu

Complexity/Performance Tradeoffs Unlicensed band + simple coord protocols Cooperative Ad-hoc, Cooperative Ad-hoc, Multi-hop Coding, Multi-hop Coding, Collaboration Signal Processing Efficient operation Internet Collaboration Signal Processing Internet Server-based Server-based requires radios that Spectrum Spectrum Etiquette Etiquette Do we wait for Moore’s law to catch up or we (degree of coordination) can: Protocol Complexity ? Radio-level s “cognitive radio” d Radio-level l e Unlicensed Discover Spectrum  h Unlicensed d Spectrum schemes n Band a Etiquette h Band Etiquette need new hardware architectures for CR? n with DCA Protocol i Self-Organize into  s with DCA Protocol U (e.g. P C (e.g. l 802.11x) e hierarchical l l 802.11x) a r a p networks y l e v Agile i Internet s “ Open Access” s Agile Internet a m Wideband Spectrum Cooperate  + smart radios r Wideband Spectrum o Radios Leasing s Reactive ’ Radios A Leasing Reactive P G Collaborate Rate/Power  F UWB, Rate/Power r UWB, e Control w Static Spread Control o p Static Spread Assignme w Spectrum o Assignme L nt Spectrum nt Hardware Complexity Problems with existing (experimental) platforms: “Analog” issues: range (frequency, power), agility, cost, future proofing   “Digital” issues: power consumption, performance vs. flexibility, cost, future proofing Ease of “use” issues: how do we program/ control these platforms?  WINLAB

Low Cost Programmable Radio (LCPR) Cost effective solution tailored for  ISM/ UNII bands  No on-board memory  Modest FPGA resources (Spartan XC3S400)  8-bit CPU  USB host transfer  Used as noise generator/ spectrum sensor in Orbit WINLAB

WARP Platform (Rice University) Xilinx Virtex-II Pro (Xilinx  XC2VP70 ) FPGA 10/ 100 Ethernet  4 Daughtercard Slots  RS-232 UART  16-bit Digital I/ O  Radio dauthercard  2 x 160MS/ s 16-bit DAC  2 x 65MS/ s 14-bit dual-ADC   dual-band ISM/ UNII RF (2400-2500MHz, 4900- 5875MHz) - MIMO capable 20 or 40MHz baseband  bandwidth Design flows: • Real-time – OFDM • Non-real-time (interfaces for MATLAB ) – SISO and MIMO WINLAB

USRP/USRP2 with GNU Radio Platform “Pentium” based SDR: Open-source GNU Radio Software - signal processing code on host computer in C+ + (including FSK, PSK, AM, ASK, NBFM. WBFM, 802.11) IF -200 MHz (80 MHz  IF 0-100 MHz (50  receive) MHz transmit) 100 MS/ s 14-bit dual (IQ)  128 MS/ s DAC  ADCs  64 MS/ s ADC 400 MS/ s 16-bit dual (IQ) USB bus (W = 8 MHz)  DACs Channelizer code in   Gigabit Ethernet (W = 25 Altera Cyclone FPGA MHz) 2 RF board slots   Bigger FPGA w/ Multipliers (Spartan 3) with 1 MB high-speed on-board SRAM and high speed serial expansion interface  1 RF board slot Selection of RF daughtercards (DC-5.9 GHz): DC-30 MHz, 50-870 MHz (Rx only), 800-2400 MHz (Rx only), 400-500 MHz, 800-1000 MHz, 1150-1450 MHz, 1500-2100 MHz, 2300-2900 MHz, 2400-2500+ 4900-5840 MHz WINLAB

WiNC2R Platform WINC2R System Two 400 MSPS, 14-bit  Xilinx Virtex-5 LX50 FPGA  A/ D channels  10/ 100/ 1000 Ethernet PHY Two 500 MSPS, 16-bit  16 MB Flash DAC channels  64 MB DDR2 SDRAM  Xilinx Virtex5, SX95T  Cypress USB 2.0 controller FPGA   10-bit LVDS receive and 1GB DDR2 DRAM  transmit interfaces 4MB QDR-II SRAM  Dual RF front-end:  8-lane PCI Express Host 12-bit 64 MS/ s ADC  Interface 12-bit 64 MS/ s DAC  ISM/ UNII RF (2.4/ 5   ISM/ UNII RF (2.4/ 5 GHz) GHz) WINLAB

Virtual Flow Pipelining Architecture  Hardware engine in charge of processing flow control  Hardware and software modules atomic modules controlled by hw engine Properties:  Low complexity (gates)   High performance Simple to program  High utilization of resources  Programmable processing of phy and higher layer at speed – target rate  500 Mbps Event driven processing model  Virtualization support for controlled sharing of processing resources across  multiprotocol flows Simple programming model  System level: combining the hw/ sw functions modules to satisfy the  protocol, performance and time constraints. Software defined function  WINLAB

Cognitive Experiments at Scale  ORBIT radio grid testbed currently supports ~15/USRP and But how do we do large scale experiments in USRP2 (GNU) radios, 100 low-cost spectrum sensors, WARP and WinC2R platforms  Plan to reach ~64 cognitive radio nodes (Q1 2009) •GENI advanced technology demonstrator of cognitive radio networks •Nation-wide (experimental) cognitive radio spectrum allocation realistic environments ? Suburban ORBIT Radio Grid 20 meters 500 meters Urban Office Current ORBIT sandbox with GNU radio 400-node Radio Grid Facility at WINLAB Tech Center 300 meters 30 meters Programmable Radio Mapping Concept for ORBIT Emulator ORBIT radio node URSP CR board WINLAB