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Contents So what is it about ? Motivation Why Chips stop working - - PDF document

How to destroy your ASIC:A beginner's guide 2/21/2012 Spoiler Alert ! What this presentation is NOT about Burn Baby Burn ! How to destroy your ASIC: A beginners' guide Diptyajit Choudhury & Pramod Ghimire Student lecture : ETI135 MS in System


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How to destroy your ASIC:A beginner's guide 2/21/2012 Diptyajit Choudhury & Pramod Ghimire 1 Burn Baby Burn !

How to destroy your ASIC: A beginners' guide

Diptyajit Choudhury & Pramod Ghimire Student lecture : ETI135

MS in System on Chip (1st year) LTH, Sweden

What this presentation is NOT about

Spoiler Alert !

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So… what is it about ?

Why Chips stop working Different reasons that we have collected! Few of them are chip level factors Others are external to the chip design And most importantly, how to avoid or correct them

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Contents

Motivation Electromigration Hot Carrier effects Electro Static Discharge CMOS Latchup Clock Skew Heat Sink Power Supply

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How to destroy your ASIC:A beginner's guide 2/21/2012 Diptyajit Choudhury & Pramod Ghimire 2 MOTIVATION

How to destroy your ASIC: A beginners' guide

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  • A matter of decades from initial design to

tapeout

  • Typically more than a year, even for small

university projects

Time

  • Non recurrent Engineering costs : Grand

total [USD]12,991,904

  • Recurring Cost per unit : [USD] 25.98

Money

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http://www.dz.ee.ethz.ch/?id=1592

Real life Cases

Pentium SRT Division Bug : $0.5 billion loss to Intel Mercury Space Probe : Veered off course due to a failure to implement distance measurement in correct units. Ariane 5 Flight 501 failure : Internal sw exception during Ariane‐5 Flight 501 failure : Internal sw exception during data conversion from 64 bit floating point to 16 bit signed integer value led to mission failure.

The corresponding exception handling mechanism contributed to the processor being shutdown (This was part of the system specification).

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7/46 Subir Roy : ASPDAC / VLSI 2002 ‐ Tutorial on "Functional Verification of SoCs"

ELECTROMIGRATION

How to destroy your ASIC: A beginners' guide

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WHAT IS IT ? Electromi gration is a process involving the net movemen t of metal atoms WHAT EFFECTS DOES IT It can cause

  • pens

and shorts in circuit interconn ections in mixed‐ WHY DOES IT The physics of electromi gration is very complex and is related to IT ? under the influence

  • f

electron flow and temperat ure. DOES IT HAVE ? mixed‐ signal ICs, even under normal

  • perating

condition s. OCCUR ? materials propertie s such as grain boundary, vacancy flux, etc.

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Illustration

http://people.ccmr.cornell.edu/~ralph/projects/emig_movies/ 21 February 2012

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Simulation results

The original resistance of the wire was 2.88ohm. A constant 0.1mA testing current was used for simulation. After 200 hours’ stress at 250° C, the change of wire resistance was 1.9

  • hms, a percentage degradation of 66%.

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IBM research in 1970

4% copper added in aluminium increased the life

  • f the interconnect by the factor of 70.

Until the late 1990s, IBM used aluminum/copper (4%) allo to interconnect comp ter circ its (4%) alloy to interconnect computer circuits. copper-based processes continue to be the state of the art for the semiconductor industry today.

http://www‐tr.watson.ibm.com/journal/50th/devices/ames.html 21 February 2012

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Avoiding Electro Migration

Reference: Peter slide on wire, slide number 9”Digital IC Course” 21 February 2012

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HOT CARRIER EFFECTS

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What is it ?

Hot‐carrier‐induced degradation of MOS transistors is caused by the injection of high‐ energy electrons and holes into the gate oxide region near the drain region near the drain. The degradation is in the form of localized

  • xide charge trapping and/or interface

generation, which gradually builds up and permanently changes the oxide‐interface charge distribution

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Mars Rover Case study

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PMOS Hot Carrier Aging lifetime is two orders of magnitude than corresponding NMOS

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PARAMETER DEGRADATION

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ELECTRO STATIC DISCHARGE

How to destroy your ASIC: A beginners' guide

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Electro…what ? Why ?

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Electro Static Discharge

A shunt device to discharge positive polarity transients A shunt device to discharge negative polarity transients A series element for current limiting

Reference: Peter slides on interconnection slide number 18 21 February 2012

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Should we be concerned ?

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Electro Static Discharge

Electrostatic discharge can happen anytime a charged conductive object approaches another conductive object. Features desirable in portable devices for ESD protection Capacity to handle high peak ESD currents Abili i d d b i i ESD ik Ability to remain undamaged by repetitive ESD strikes Minimal size Minimal reverse leakage current

Source: http://www.semtech.com/circuit-protection/What-is-ESD-Protection/index.html

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Area‐Efficient CMOS Output Buffer

There are one PTLSCR Device (PMOS trigger lateral SCR) and one NTLSCR device used to effectively protect CMOS

  • utput buffer against the four‐mode ESD

stresses. In PTLSCR (NTLSCR) structure. there is a shortchannel thin‐oxide PMOS (NMOS) device inserted into the lateral SCR

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structure. This PMOS (NMOS) device with its drain made across the junction between N‐well and P‐substrate is used to triggered on the lateral SCR structure at its drain snapback‐breakdown voltage under the ESD‐stress conditions.

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Results : Evaluation

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CMOS LATCHUP

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Illustration

Reference:Digital Integrated Circuits, A design Perspective , second edition, Rabaey ,Chandrakasan, Nikolic,page no 116 21 February 2012

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Description

The combination of the wells and substrates results in the formation of parasitic n‐p‐n‐p structures Triggering these thyristor like devices leads to a shorting of the VDD and VSS lines. Resulting in a destruction of the chip, or at best a system failure that can only be resolved by a power‐down

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Reduction

To avoid Latchup, the resistance Rwelland Rpsubsshould be minimized. According to the book in recent years process innovations According to the book, in recent years, process innovations and improved design techniques have all but eliminated the risk for Latchup.

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CLOCK SKEW

How to destroy your ASIC: A beginners' guide

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What is it ?

Difference in clock signal arrival times across the chip is called clock skew Clocking sequentially‐adjacent registers on the same edge of a high‐skew clock can potentially high skew clock can potentially cause timing violations or even functional failures. Probably this is one of the largest sources of design failure in an ASIC.

Reference:http://www.eetimes.com/ContentEETimes/Doc uments/EDADesignline/201201/Chapter2_Clocks_Re sets‐04.pdf

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Minimization

1]Adding Delay in Data Path General Clock Distribution Tree has a relatively high clock skew Balanced Clock Net Balanced Clock Net H‐Tree X‐Tree Distributed Buffers

Reference:Peter slides on Timing and clocking slide no 5- 7

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Other Methods

2] Clock Reversing in a circular structure 3]Clocking on alternate Edges

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4]Ripple clocking Structures

Three bit ripple down‐counter

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HEAT SINK

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Our own experiences

All modern CPU requires Heat sink! Passive Heat Sink(without a fan) Active Heat sink(with fan) Active Heat sink(with fan) The computer/laptop or device will hang and shutdown Ultimately, the system will crash, hardware is damaged Processor has to be replaced alongwith the heat sink in many cases.

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What does it imply ?

To further enhance thermal dissipation of the package in

  • rder to maintain die junction temperature, an external heat

sink is typically required. For ease of assembly and product field reliability, mechanical screw mounting of the heat sink is preferred, especially for large package. This costs more area and causes reliability problems, hence an adhesive heat sink attachment method is preferred for asic solutions

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CPU Without Heat Sink

http://www.youtube.com/watch?feature=endscreen&v=BSGcnRanYMM&NR=1 21 February 2012 Diptyajit Choudhury & Pramod Ghimire

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High Voltage to chip

http://datacent.com/datarecovery/hdd/western_digital 21 February 2012

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How to be sure that this doesn’t happen to you ?

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A look at Reliability Tests : Different types

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CONCLUSION

Different factors NASA case study IBM case study Links to few videos

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References

1. Harry, C.C.; Mathiowetz, C.H.; , "ASIC reliability and qualification: a user's perspective," Proceedings of the IEEE , vol.81, no.5, pp.759‐767, May 1993 2. Jie Xue; Hubbard, K.; Li, P.; Tang, J.; Poom, J.; Brillhart, M.; Alcoe, D.; Kunz, R.; Mendez, D.; , "Evaluation of manufacturing assembly process impact on long term reliability of a high performance ASIC using flip chip hyperBGA pacuage," Electronic Components and Technology Conference, 2003. Proceedings. 53rd , vol., no., pp. 359‐ 364, May 27‐30, 2003 3. Meloth, S.; , "ESD protection methods in Ethernet based embedded systems," Electromagnetic Interference & Compatibility, 2008. INCEMIC 2008. 10th International Conference on , vol., no., pp.189‐ 194, 26‐27 Nov. 2008 4. Ming‐Dou Ker; Kuo‐Feng Wang; Mei‐Chu Joe; Yuan‐Hua Chu; Tain‐Shun Wu; , "Area‐efficient CMOS output buffer with enhanced high ESD reliability for deep submicron CMOS ASIC " ASIC Conference and Exhibit buffer with enhanced high ESD reliability for deep submicron CMOS ASIC, ASIC Conference and Exhibit, 1995., Proceedings of the Eighth Annual IEEE International , vol., no., pp.123‐126, 18‐22 Sep 1995 5. Xiangdong Xuan; Chatterjee, A.; , "Sensitivity and reliability evaluation for mixed‐signal ICs under electromigration and hot‐carrier effects," Defect and Fault Tolerance in VLSI Systems, 2001. Proceedings. 2001 IEEE International Symposium on , vol., no., pp.323‐328, 2001 6. Xiangdong Xuan; Chatterjee, A.; Singh, A.D.; , "ARET for system‐level IC reliability simulation," Reliability Physics Symposium Proceedings, 2003. 41st Annual. 2003 IEEE International , vol., no., pp. 572‐ 573, 30 March‐4 April 2003 7. Yuan Chen; Mojaradi, M.; Westergard, L.; Billman, C.; Cozy, S.; Burke, G.; Kolawa, E.; , "Design for ASIC reliability for low‐temperature applications," Integrated Reliability Workshop Final Report, 2005 IEEE International , vol., no., pp. 5 pp., 17‐20 Oct. 2005

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Other sources

  • 1. http://www‐glast.slac.stanford.edu/lat‐

details/Engineering%20Meetings/GLAST%20 ASIC%20SLAC%20ESD%20Presentation1.pdf

  • 2. Several of Peter’s slides both from this course

and the previous one.

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THANK YOU

Questions?