CPSC 121: Models of Computation Instructor: Bob Woodham - - PowerPoint PPT Presentation

CPSC 121: Models of Computation

Instructor: Bob Woodham woodham@cs.ubc.ca

Department of Computer Science University of British Columbia

Lecture Notes 2008/2009, Section 203

CPSC 121: Models of Computation

Menu February 6, 2009

Topics: Overflow in n-Bit Binary Addition/Subtraction (revisited) (More) Examples (cont’d) Reading: Next: Epp 3.1, Theorem 3.4.1 (page 157), Representation of Integers (pages 159–163), Epp 3.6, and 3.7 Reminders: On-line Quiz 7 deadline 9:00pm February 8 Assignment 2 due Friday, February 13 (by 17:00) Marked Assignment 1 available in tutorials Midterm exam Tuesday, February 24 (evening) READ the WebCT Vista course announcements board

CPSC 121: Models of Computation

4-Bit Adder

Consider the following high-level design for a “chip” for adding 4 bit integers a and b The 4 bit output s = a + b

4−bit adder c s0 s1 s2 s3 b0 b1 b2 b3 a0 a1 a2 a3

• ut

c

in

We’ll need (and the figure shows) two more wires: 1 additional input, cin, and 1 additional output, cout

CPSC 121: Models of Computation

Detecting Overflow in n-Bit Binary Addition

Case 1: Adding 2 unsigned integers Check if the last carry, cn−1, is one Case 2: Adding 2 signed integers A simple check of last carry, cn−1, doesn’t work RECALL: Ignoring carry is key to 2’s complement

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition

Let s = a + b Note 1: It’s not possible to produce overflow when adding integers of opposite sign (i.e., when the MSBs of a and b differ). The result, s, is either less positive than the most positive of a and b or less negative than the most negative of a and b (i.e., it’s closer to zero) Note 2: There are two kind’s of overflow:

1

The result is too positive (i.e., a > 0, b > 0, s < 0). In this case, the MSBs are, respectively, an−1 = bn−1 = 0; sn−1 = 1

2

The result is too negative (i.e., a < 0, b < 0, s > 0). In this case, the MSBs are, respectively, an−1 = bn−1 = 1; sn−1 = 0

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d)

We can put this into a truth table: an−1 bn−1 sn−1 Overflow 1 1 1 1 1 1 1 1 1 1 1 1 1 1 By inspection of the truth table, we see we get overflow if and

• nly if an−1 = bn−1 and bn−1 = sn−1. Thus, a proposition for
• verflow is

(an−1 ↔ bn−1) ∧ (bn−1 ⊕ sn−1)

CPSC 121: Models of Computation

Overflow in n-Bit Signed Binary Addition (cont’d)

We can implement this as a circuit:

• verflow

sn−1 bn−1 an−1

CPSC 121: Models of Computation

Summary: Arithmetic Overflow (So Far)

Quick Review: So far, we’ve dealt with 3 cases:

1

Unsigned addition. (Check cout)

2

Signed addition. (Circuit based on an−1, bn−1, sn−1)

3

Signed subtraction. (Circuit based on an−1, bn−1, sn−1) But, there’s a 4th case:

4

Negation Recall, for n-bit signed integers, the numbers represented range from −2n−1 to 2n−1 − 1 The negation of −2n−1 can not be represented Again, we get overflow

CPSC 121: Models of Computation

Overflow in n-Bit Binary Negation

A circuit to check for this case of overflow is quite simple. We detect the case b = −2n−1 = 1000 . . . 02 explicitly

• verflow

b0 b1 b2 bn−2 bn−1

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

In order to choose between the 4 overflow conditions, we design a 2-bit code, c1c0, as follows: c1 c0

• peration

unsigned addition 1 signed addition 1 signed subtraction 1 1 negate b Think of these 2 bits as “control bits”

CPSC 121: Models of Computation

Example: Arithmetic Overflow Re-Visited

Now, here’s the circuit:

CPSC 121: Models of Computation

A Circuit of Moderate Complexity

Control bits: 00 = unsigned addition 01 = signed addition 10 = signed subtraction 11 = negate b (ignore a)

CPSC 121: Models of Computation