CSEE 3827: Fundamentals of Computer Systems Single Cycle MIPS - - PowerPoint PPT Presentation

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CSEE 3827: Fundamentals of Computer Systems Single Cycle MIPS - - PowerPoint PPT Presentation

Nov 06, 2023 209 likes •528 views

CSEE 3827: Fundamentals of Computer Systems Single Cycle MIPS Implementation Outline We will examine two MIPS implementations A single-cycle version A pipelined version Simple subset of MIPS, showing most aspects Memory

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SLIDE 1

CSEE 3827: Fundamentals of Computer Systems

Single Cycle MIPS Implementation

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SLIDE 2

Outline

  • We will examine two MIPS implementations
  • A single-cycle version
  • A pipelined version
  • Simple subset of MIPS, showing most aspects
  • Memory reference: lw, sw
  • Arithmetic/logical: add, sub, and, or, slt
  • Control transfer: beq, j
  • Next unit: CPU performance factors
  • Instruction count (determined by ISA and compiler)
  • Cycles per instruction and cycle time (determined by CPU hardware)

2

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SLIDE 3

Instruction Execution

  • PC → instruction memory, fetch instruction
  • Register numbers → register file, read registers
  • Depending on instruction class:
  • Use ALU to calculate:
  • Arithmetic or logical result
  • Memory address for load/store
  • Branch target address
  • Access data for load/store
  • PC ← target address or PC + 4

3

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CPU Overview

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Can’t just join wires together, use muxes

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Controller generates selects for the Muxes (and some other stuff)

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Combinational Elements

  • AND gate (Y = A & B)
  • Multiplexer (Y = S ? A : B)

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  • Adder (Y = A + B)
  • Arithmetic/Logic Unit (ALU)

A B Y A B Y A B Y F (Y = F(A,B)) A B Y S

+

ALU

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SLIDE 8

Clocking Methodology

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Combinational logic transforms data during clock cycles. Longest combinational delay determines clock period.

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SLIDE 9

Building a datapath incrementally

  • Datapath: elements that process data and addresses in the CPU
  • Datapath will execute one instruction in one clock cycle
  • Each datapath element can only do one function at a time
  • Hence, we need separate instruction and data memories
  • Use multiplexers where alternate data sources are used for different

instructions

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Instruction Fetch

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  • Fetch Instruction contained in PC register from memory
  • Compute PC + 4 for next instruction
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Part 1: Instruction Fetch

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R-Format Instructions

  • Read two register operands
  • Perform arithmetic/logical operation
  • Write register result

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Load/Store Instructions

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  • Read register operands
  • Calculate address using 16-bit offset (sign-extend offset and use ALU)
  • Load: read memory and update register
  • Store: write register value to memory
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SLIDE 14

Part 2: R-Type/Load/Store Datapath

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SLIDE 15

Branch Instructions

  • Read register operands
  • Compare operands (use ALU: subtract and check zero output)
  • Calculate target address
  • Sign-extend displacement
  • Shift left two places (word displacement)
  • Add to PC+4 (already calculated by instruction fetch)

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Part 3: Instruction Fetch w. Branch

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Full Datapath

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Datapath Control Scheme

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  • Main control controls whole

datapath based on opcode

ALU control controls ALU based on opcode (ALUOp) and function field (funct)

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SLIDE 19

ALU Control Inputs/Outputs

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R-type 10 lw 00 sw 00 beq 01 0000 AND 0001 OR 0010 add 0110 subtract 0111 set on less than Instruction[5:0]

Main Control

ALUOp Operation 2 4

ALU

ALU control

(See Appendix C of text for implementation of corresponding ALU.)

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SLIDE 20

ALU Control Implementation

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lw sw beq R-type R-type R-type R-type R-type → 00 → 00 → 01 → 10 → 10 → 10 → 10 → 10 xxxxxx → load word xxxxxx → store word xxxxxx → branch equal 100000 → add 100010 → subtract 100100 → AND 100101 → OR 101010 → set on less than → add → add → subtract → add → subtract → AND → OR → set on less than → 0010 → 0010 → 0110 → 0010 → 0110 → 0000 → 0001 → 0111

  • p

c

  • d

e A L U O p f r

  • m

m a i n c

  • n

t r

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I n s t r u c t i

  • n

[ 5 : ] O p e r a t i

  • n
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ALU Control Truth Table

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xxxxxx xxxxxx xxxxxx 100000 100010 100100 100101 101010 0010 0010 0110 0010 0110 0000 0001 0111

A L U O p f r

  • m

m a i n c

  • n

t r

  • l

I n s t r u c t i

  • n

[ 5 : ] O p e r a t i

  • n

00 00 01 10 10 10 10 10

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ALU Control Truth Table 2

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Datapath Control Scheme

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Main control signals derive from instruction types

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rs rt rd shamt funct

31:26 25:21 20:16 15:11 10:6 5:0

35 or 43 rs rt constant

15:0

4 rs rt constant

15:0

R-type: Load/Store: Branch:

31:26 25:21 20:16 31:26 25:21 20:16

always read read, except for load write for R-type and load sign-extend and add

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SLIDE 25

R-Type Control Signals

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10 1 1

(Alt. illustration: Fig. 4.19)

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SLIDE 26

lw Control Signals

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00 1 1 1 1

(Alt. illustration: Fig. 4.20)

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sw Control Signals

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1 00 x x 1

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beq Control Signals

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1 01 x x

(Alt. illustration: Fig. 4.21)

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Main Control Truth Table

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  • 000000

100011 101011 000100

Instruction[31:26]

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SLIDE 30
  • Unconditional jump to instruction at label
  • Instruction encoded in J-type format
  • Jump uses word addresses
  • Update PC with concatenation of:
  • Top 4 bits of old PC
  • 26-bit jump address
  • 00

The j instruction

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2 address

j label

25:0 31:26

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SLIDE 31

Implementing the jump instruction

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