Design Optimization of Multi-Cluster Embedded Systems for Real-Time - - PowerPoint PPT Presentation

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Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications

Paul Pop, Petru Eles, Zebo Peng, Viaceslav Izosimov Embedded Systems Lab (ESLAB) Linköping University, Sweden Magnus Hellring, Olof Bridal

• Dept. of Electronics and Software

Volvo Technology Corp., Göteborg, Sweden

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... ... Factory Systems

Heterogeneous Networks

Distributed Heterogeneous System

... Heterogeneous Networks Multi-Cluster Systems ... NoCs Automotive Electronics ...

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Distributed Safety-Critical Applications

... ...

Gateway

• Applications distributed over heterogeneous networks are difficult to...

Analyze (guaranteeing timing constraints) Design (partitioning, mapping, bus access optimization)

• Applications distributed over

the heterogeneous networks

Reduce costs: use resources efficiently Requirements: close to sensors/actuators [DATE’03] This paper!

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Outline

Motivation System architecture and application model Scheduling for multi-clusters [DATE’03] Design optimization problems

Partitioning Mapping Bus access optimization

Optimization strategy Experimental results Contributions and Message

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S0 S1 S2 SG S0 S1 S2 SG TDMA Round Cycle of two rounds Slot

Time Triggered Protocol (TTP)

• Bus access scheme:

time-division multiple-access (TDMA)

• Schedule table located in each TTP

controller: message descriptor list (MEDL)

Controller Area Network (CAN)

• Priority bus, collision avoidance
• Highest priority message

wins the contention

• Priorities encoded in the frame identifier

Hardware Architecture

Gateway

... ...

Time-triggered cluster

Static cyclic scheduling Time-triggered protocol

Event-triggered cluster

Fixed priority preemptive scheduling Controller area network protocol

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CPU

NG

OutCAN

TTP Controller

S1 SG Round2

P4 P1 CPU

N1

TTP Controller

MBI

CPU

MBI

CAN Controller CPU

N2 CAN Controller

T

m1 m2 m1 S1 SG

OutTTP

T P2 P3

OutN2

m3 m3

Software Architecture

...

...

Time-triggered cluster Event-triggered cluster Gateway

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Multi-Cluster Scheduling [DATE’03]

Application, Partitioning, Mapping, Architecture TT Bus Configuration Priorities Schedule Tables Response times Static Scheduling Multi-Cluster Scheduling Offsets Response Times Response Time Analysis

MultiClusterScheduling algorithm

Schedulability analysis: communication delays through the gateway Scheduling: cannot be addressed separately for each cluster

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Problem Formulation

Input

System architecture Application Partial partitioning and mapping, based on the designer’s experience

Application: set of process graphs

... ...

Architecture: Multi-cluster

Output

Design implementation such that the application is schedulable

Partitioning for each un-partitioned process Mapping for each un-mapped process Priorities for ET messages TDMA slot sequence and sizes for the TT bus Priorities for ET processes Schedule table for TT messages

Partitioning and mapping Communication infrastructure Scheduling information

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P4 P5 P3 P6 P2 P1 N1 Missed (faster) N2 (slower) N3 Met

Motivational Example #1/1

N2 N3 TTC ETC N1 CAN TTP P3 P6 P5 P4 P2 P1 P1 P2 P3 P4 N1 N2 X X X 50 70 40 90 X P5 X 40 N3 P6 70 X X X X X 40 X Deadline for P6 Deadline for P5

In which cluster to place process P4?

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P4 P5 P3 P6 P2 P1 N1 Missed (faster) N2 (slower) N3 Met

Motivational Example #1/2

N2 N3 TTC ETC N1 CAN TTP P3 P6 P5 P4 P2 P1 P1 P2 P3 P4 N1 N2 X X X 50 70 40 90 X P5 X 40 N3 P6 70 X X X X X 40 X P4 P5 P3 P6 P2 P1 N1 P4 Preempted (faster) N2 (slower) N3 Met Met Preemption not allowed Deadline for P6 Deadline for P5

In which cluster to place process P4?

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P4 P5 P3 P6 P2 P1 N1 Missed (faster) N2 (slower) N3 Met

Motivational Example #1/3

N2 N3 TTC ETC N1 CAN TTP P3 P6 P5 P4 P2 P1 P1 P2 P3 P4 N1 N2 X X X 50 70 40 90 X P5 X 40 N3 P6 70 X X X X X 40 X P4 P5 P3 P6 P2 P1 N1 P4 Preempted (faster) N2 (slower) N3 Met Met Preemption not allowed P3 P4 P4 P6 P5 P2 P1 N1 Preempted (faster) N2 (slower) N3 Met Met Deadline for P6 Deadline for P5

In which cluster to place process P4?

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P1 N1 P3 TTP S2 N2 S3 SG SG S3 S1 SG P2 Missed S2 S3 S1 m1 m2 N3 CAN NG N4

Motivational Example #2/1

P1 P3 P2 m1 m2 P1 P2 P3 N1 N2 20 X X X 40 X N4 X 50 X N3 X X 20 N3 N4 TTC ETC N2 CAN TTP N1 NG

Where to map process P2?

Deadline

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P1 N1 P3 TTP S2 N2 S3 SG SG S3 S1 SG P2 Missed S2 S3 S1 m1 m2 N3 CAN NG N4

Motivational Example #2/2

P1 P3 P2 m1 m2 P1 P2 P3 N1 N2 20 X X X 40 X N4 X 50 X N3 X X 20 N3 N4 TTC ETC N2 CAN TTP N1 NG

Where to map process P2?

Met P1 N1 P3 TTP S2 T CAN N4 P2 NG S2 SG S2 S3 S1 SG T S2 S3 S1 N4 N3 m1 m1 m2 m2 N2 Deadline

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Motivational Example #3/1

P1 N1 P4 TTP S1 T CAN N2 P2 NG SG m1 SG S1 T m2 T P3 T S1 SG m4 S1 SG m3 Round 4 Missed m1 m3 m2 m4

What are the priorities on ETC? Which slot should come first on the TTC?

P1 P2 P3 P4 N1 N2 20 X X X 40 40 X 20 P1 P4 P2 P3 m1 m2 m3 m4 N1 N2 TTC CAN TTP ETC Deadline

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Motivational Example #3/2

P1 N1 P4 TTP S1 T CAN N2 P2 NG SG m1 SG S1 T m2 T P3 T S1 SG m4 S1 SG m3 Round 4 Missed m1 m3 m2 m4

What are the priorities on ETC? Which slot should come first on the TTC?

P1 P2 P3 P4 N1 N2 20 X X X 40 40 X 20 P1 P4 P2 P3 m1 m2 m3 m4 N1 N2 TTC CAN TTP ETC P1 N1 P4 TTP S1 T CAN N2 P2 NG SG m1 SG S1 T m2 T P3 T S1 SG SG Missed m1 m2 m3 m4 m3 m4 Deadline

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Motivational Example #3/3

P1 N1 P4 TTP S1 T CAN N2 P2 NG SG m1 SG S1 T m2 T P3 T S1 SG m4 S1 SG m3 Round 4 Missed m1 m3 m2 m4

What are the priorities on ETC? Which slot should come first on the TTC?

P1 P2 P3 P4 N1 N2 20 X X X 40 40 X 20 P1 P4 P2 P3 m1 m2 m3 m4 N1 N2 TTC CAN TTP ETC P1 N1 P4 TTP S1 T CAN N2 P2 NG SG m1 SG S1 T m2 T P3 T S1 SG SG Missed m1 m2 m3 m4 m3 m4 P1 N1 P4 TTP SG T CAN N2 P2 NG S1 T T P3 S1 SG S1 SG m4 m3 Met Round 1 m2 m1 m4 m3 m1 m2 Deadline

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Optimization Strategy

• Multi-Cluster Configuration
• 1. Initial Partitioninig and Mapping
• Determines an initial partitioning and mapping
• List scheduling-based greedy approach
• Priority of ready processes: critical path
• 2. Partitioning and Mapping Heuristic
• Iteratively improves on the initial partitioning and mapping
• Intelligent design transformations that improve schedulability
• Based on feedback from MultiClusterScheduling
• 3. Bus Access Optimization
• Determines the slot sequence and lengths on the TTC,

message priorities on the ETC

• Greedy optimization heuristic
• Straightforward solution
• Partitioning and mapping that balances the utilization of processors and buses
• Could be produced by a designer without optimzation tools

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Experimental Results

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 50 100 150 200 250

Percentage schedulable applications [%] Number of processes Can we increase the number of schedulable applications? Straightforward solution Bus Access Optimization Partitioning and Mapping Heuristic Initial Partitioning and Mapping

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Experimental Results, Cont.

How time-consuming is our optimization strategy?

0:00 0:20 0:40 1:00 1:20 1:40 2:00 2:20 2:40 3:00 3:20 3:40 4:00 4:20 4:40 5:00 5:20 50 100 150 200 250

Average execution time [hours:minutes] Number of processes Multi-Cluster Configuration Partitioning and Mapping Heuristic Initial Partitioning and Mapping Bus Access Optimization

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Contributions and Message

Contributions

Addressed design problems characteristic to multi-clusters

Partitioning Mapping Bus Access Optimization

Proposed heuristics for design optimization

Analysis and optimization methods are needed for the efficient implementation of applications distributed over interconnected heterogeneous networks.