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- Intro. VLSI: CMOS inverter
Digital System Design for Circuit and Electronics Additional - - PowerPoint PPT Presentation
Digital System Design for Circuit and Electronics Additional - - PowerPoint PPT Presentation
Digital System Design for Circuit and Electronics Additional material Intro. VLSI: CMOS inverter CMOS inverter: black and white representation A counter layout Rules for design rule checking: basic rules Rules for composition Concept of
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CMOS inverter: black and white representation
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A counter layout
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Rules for design rule checking: basic rules
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Rules for composition
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Concept of the State Machine Example: Odd Parity Checker Next State/Output Functions NS = PS xor PI; OUT = PS
D R Q Q Input CLK PS/Output \Reset NS
D FF Implementation
T R Q Q Input CLK Output \Reset
T FF Implementation Timing Behavior: Input 1 0 0 1 1 0 1 0 1 1 1 0
Clk Output Input 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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State Behavior of R-S Latch Truth Table Summary
- f R-S Latch Behavior
Q hold 1 unstable S 1 1 R 1 1
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Sequential Switching Networks Edge triggered device sample inputs on the event edge 7474 Bubble here for negative edge triggered device
Positive edge-triggered flip-flop D Q Clk
D-FlipFlop
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In Q Q
1
Clk 100
Cascaded Flipflops and Setup/Hold/Propagation Delays Shift Register S,R are preset, preclear New value to first stage while second stage
- btains current value
- f first stage
Correct Operation, assuming positive edge triggered FF
IN CLK Q0 Q1 D C Q Q D C Q Q
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Design Procedure
Excitation Tables: What are the necessary inputs to cause a particular kind of change in state?
D 1 1 T 1 1 Q
+
1 1 Q 1 1 S 1 X R X 1 K X X 1 J 1 X X
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Design problem
- Please design a sequence recognizer of
1011, using first a RS flip-flop, then a D flip flop.
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Results
X 1 00 Y1 Y2 1 01 1 10 1 11 1 X 1 00 1 01 1 10 1 11 1
Input = X D = X S = X’Y1’ Y2 R = X’Y1Y2’ + X Y1 Y2 Z = X Y1 Y2 (output)
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Circuit of 1011 recognizer
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