Dr. CU 2.0: A Scalable Detailed Routing Framework with - - PowerPoint PPT Presentation

• Dr. CU 2.0: A Scalable Detailed Routing Framework

with Correct-by-Construction Design Rule Satisfaction∗

Haocheng Li, Gengjie Chen, Bentian Jiang, Jingsong Chen, Evangeline F. Y. Young

∗Source code is available at htps://github.com/cuhk-eda/dr-cu.

1 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

2 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

3 / 26

Detailed Routing

Figure 1: Qad-Core Design [Liu et al. 2019].

◮ 1M nets in 20K × 20K × 10 grid points, hardly routed by ILP-based a or SAT-based b methods. ◮ Complicated design rules:

◮ Parallel run length (PRL) spacing c. ◮ End-of-line (EOL) spacing. ◮ EOL spacing with parallel edges d. ◮ Corner-to-corner (C2C) spacing e.

a[Kahng, Wang, and Xu 2018] b[Park et al. 2019] c[Qi, Cai, and Zhou 2015] d[Yu et al. 2015] e[Côté, Pierrat, and Hurat 2004]

3 / 26

Problem Formulation

Given ◮ technology node and design rules, ◮ placement result with netlist, ◮ routing tracks and blockages, and ◮ route guides generated from global routing, route all nets minimizing a weighted sum of ◮ total wire-length and via count, ◮ out-of-guide, off-track, wrong-way usage, and ◮ design rule violations.

4 / 26

Contributions

For Each Rip-up and Reroute Iteration

Access Point Assignment Multi-threaded Maze Routing Multi-threaded Via Selection Post-routing Refinement Figure 2: Detailed Routing Flow.

◮ Compute valid access points of each pin and create off-track vias if no same-layer access point is valid. ◮ Handle end-of-line spacing with parallel edges in a correct-by-construction manner. ◮ Fix corner-to-corner spacing violations in post-processing. ◮ Develop a lookup-table-based via insertion method and select violation-free via types from the cell library.

5 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

6 / 26

Two-Level Sparse Data Structures

routing region of a net routing topology local grid graph global grid graph

record edge usage maze route query cache

Figure 3: Global and Local Grid Graph.

6 / 26

Parallel Run Length Spacing

R1 R2 R2 R2 w2 w1 lt lb sb sm st

Figure 4: Parallel Run Length Spacing.

The parallel run length (PRL) spacing requirements between two wires of different nets depend on both width and PRL of the two wires.

7 / 26

End-of-line Spacing

Figure 5: Example of Triple Paterning Layout Decomposition †.

eolWithin eolWidth eolSpace Metal EOL Spacing

Figure 6: EOL Spacing without Parallel Edges.

eolWithin eolWidth eolSpace Metal EOL Spacing parSpace eolWithin parWithin Parallel Edge Region

Figure 7: EOL Spacing with Parallel Edges.

†[Yu et al. 2015]

8 / 26

Corner-to-Corner Spacing

w ≤ eolWidth

Figure 8: C2C spacing does not apply.

w > eolWidth

Figure 9: C2C spacing applies.

9 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

10 / 26

Local Grid Graph Construction

Metal 1 Metal 2

(a) Before Expansion. (b) Afer Expansion.

Figure 10: Unconnected Route Guides.

◮ Expand route guides in preferred routing direction for full connections. ◮ Expand in x- and y-direction for each rip-up-and-reroute iteration. ◮ Extend to adjacent layers if the numbers of violations exceed a threshold.

10 / 26

Pin Access

◮ Assign same-layer surrounding grid points as access points by default. ◮ Use diff-layer access points by an off-track via if no valid same-layer access points. ◮ Penalize other nets for using grid points above/below it before it is connected.

D SI SE OBS

Figure 11: No valid same-layer access point.

D SI SE OBS

Figure 12: Use off-track via

11 / 26

Via Type Selection Flow

For Each Rip-up and Reroute Iteration

LUT Construction Multi-threaded Via Locationing Multi-threaded Type Selection Post-routing Type Selection Figure 13: Detailed Routing Flow.

◮ Construct via conflict lookup tables (LUTs). ◮ Determine via locations and generate routing topology for a net. ◮ Perform via type selection for the net. ◮ Finally decide via type globally in a post refinement stage.

12 / 26

Via Conflict Lookup Table

◮ Via-pin/obstacle conflicts. ◮ Via-wire conflicts. ◮ Via-via conflicts.

M3 track M4 track candidate via using via type 1 conflict w.r.t. neighboring via using via type 2 violation-free locations forbidden locations/region neighboring via using via type 2

Figure 14: Via-via LUT.

13 / 26

Pessimistic Lookup Table

◮ Checking every via-type during routing is time-consuming. ◮ Merged LUTs records all suspicious conflicts. ◮ Suspicious conflicts can be verified when the via types are determined.

M3 track M4 track candidate via using via type 1 conflict w.r.t. via using via type 1 conflict w.r.t. via using via type 2 conflict w.r.t. via using via type 3 violation-free locations forbidden regions union

Figure 15: Merged Via-via LUT.

14 / 26

Parallel Run Length Spacing Handling

R1 R2 R2 R2 w2 w1 lt lb sb sm st

Figure 16: Parallel Run Length Spacing. Figure 17: Spacing Table

Parallel Run Length 0.00 0.22 0.47 0.63 1.50 Width 0.00 0.05 0.05 0.05 0.05 0.05 0.09 0.05 0.06 0.06 0.06 0.06 0.16 0.05 0.10 0.10 0.10 0.10 0.47 0.05 0.10 0.13 0.13 0.13 0.63 0.05 0.10 0.13 0.15 0.15 1.50 0.05 0.10 0.13 0.15 0.50 Penalize some tracks along power and ground rails.

15 / 26

End-of-line Spacing Handling

Assume that a parallel edge exist to avoid blocking neighboring tracks.

eolWithin eolWidth eolSpace Metal EOL Spacing

Figure 18: EOL Spacing without Parallel Edges.

eolWithin eolWidth eolSpace Metal EOL Spacing parSpace eolWithin parWithin Parallel Edge Region

Figure 19: EOL Spacing with Parallel Edges.

16 / 26

Corner-to-Corner Spacing Handling

Slightly extend an on-track wire segment that connects a wrong-way wire segment.

w > eolWidth

(a)

w ≤ eolWidth

(b) (c) (d)

Figure 20: (a) Via applied to C2C. (b) Via not applied to C2C. (c) Wrong-way wire applied to C2C. (d) Wrong-way wire not applied to C2C.

17 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

18 / 26

Comparison with 1st in ISPD 2019 Contest ‡

0.5 1 1.5 # Short # PRL Score Time

1 1 1 1 1.37 1.08 1.02 0.67

Average Ratio 1st Ours 1 2 ·108

9t1 9t2 9t3 9t4 9t5 9t6 9t7 9t8 9t9 9t10

Score 1st Ours

‡[Liu et al. 2019] 18 / 26

Comparison with 1st in ISPD 2019 Contest §

2,000 4,000 6,000 8,000

9t1 9t2 9t3 9t4 9t5 9t6 9t7 9t8 9t9 9t10

Number of Shorts 1st Ours 1 2 ·104

9t1 9t2 9t3 9t4 9t5 9t6 9t7 9t8 9t9 9t10

Number of PRLs 1st Ours

§[Liu et al. 2019] 19 / 26

Comparison with [Chen et al. 2019]

1 2 Score Time

1 1 1.69 0.85

Average Ratio Chen Ours 0.5 1 ·108

8t1 8t2 8t3 8t4 8t5 8t6 8t7 8t8 8t9 8t10

Score Chen Ours

20 / 26

Comparison with [Chen et al. 2019]

0.5 1 1.5 ·105

8t1 8t2 8t3 8t4 8t5 8t6 8t7 8t8 8t9 8t10

Short Area Chen Ours 1 2 ·104

8t1 8t2 8t3 8t4 8t5 8t6 8t7 8t8 8t9 8t10

Number of Spacing Violations Chen Ours

21 / 26

Comparison between Different Setings

100 200

9t1 9t2 9t3 9t4 9t5 9t6 9t7 9t8 9t9 9t10

ISPD’19 Qality Score (×106)

(a) Upper-layer Access Points with Off-track Vias.

wo/ upper access w/ upper access 100 200

9t1 9t2 9t3 9t4 9t5 9t6 9t7 9t8 9t9 9t10

ISPD’19 Qality Score (×106)

(b) Layer Expansion of Local Grid Graphs.

wo/ layer expansion w/ layer expansion

22 / 26

Outline

Introduction Preliminary Algorithms Experimental Results Conclusion

23 / 26

Conclusion

◮ Compute valid access points of each pin and create off-track vias. ◮ Handle end-of-line spacing with parallel edges during routing. ◮ Fix corner-to-corner spacing violations in post-processing. ◮ Develop a lookup-table-based via insertion method.

23 / 26

Thanks! Qestions?

24 / 26

References I

Chen, Gengjie, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, and Evangeline FY Young (2019). “Detailed routing by sparse grid graph and minimum-area-captured path search”. In: Proceedings of the 24th Asia and South Pacific Design Automation Conference. ACM, pp. 754–760. Côté, Michel Luc, Christophe Pierrat, and Philippe Hurat (Oct. 2004). Accelerated layout processing using OPC pre-processing. US Patent 6,807,663. Kahng, Andrew B, Lutong Wang, and Bangqi Xu (2018). “TritonRoute: an initial detailed router for advanced VLSI technologies”. In: IEEE/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, pp. 1–8. Liu, Wen-Hao, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, and Gracieli Posser (2019). “ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules”. In: Proceedings of the 2019 International Symposium on Physical Design. ACM, pp. 147–151.

25 / 26

References II

Park, Dongwon, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, and Chung-Kuan Cheng (2019). “ROAD: Routability Analysis and Diagnosis Framework Based on SAT Techniques.”. In: ACM International Symposium on Physical Design (ISPD), pp. 65–72. Qi, Zhong-Dong, Yi-Ci Cai, and Qiang Zhou (2015). “Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths”. In: Journal of Computer Science and Technology 30.3, pp. 614–628. Yu, Bei, Kun Yuan, Duo Ding, and David Z. Pan (Mar. 2015). “Layout Decomposition for Triple Paterning Lithography”. In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) 34.3, pp. 433–446.

26 / 26