Energy Reduction via Critical Path Prediction Toshinori Sato - - PowerPoint PPT Presentation

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Energy Reduction via Critical Path Prediction Toshinori Sato - - PowerPoint PPT Presentation

Nov 29, 2022 27 likes •308 views

Energy Reduction via Critical Path Prediction Toshinori Sato Akihiro Chiyonobu Itsujiro Arita Kyushu Institute of Technology WCED'02 The KIT COSMOS Processor 1 Overview Background Power of CMOS circuits Device and circuit design

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WCED'02 The KIT COSMOS Processor 1

Energy Reduction via Critical Path Prediction

Toshinori Sato Akihiro Chiyonobu Itsujiro Arita Kyushu Institute of Technology

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WCED'02 The KIT COSMOS Processor 2

Overview

Background Power of CMOS circuits Device and circuit design techniques Architectural-level design techniques

Criticality-based instruction scheduling Clustered microarchitecture

Summary

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WCED'02 The KIT COSMOS Processor 3

Nanometer design

Nanometer design poses many

challenges for processor designers.

reliability, signal integrity, speed, power…

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WCED'02 The KIT COSMOS Processor 4

Applications

Current trend of increasing popularity of

mobile devices such as smart cell phones is a driving force to investigate high-performance and energy-efficient microprocessors.

3D video games, flight ticket reservation, mobile banking,

mobile trading, digital camera, MP3 player …

As computing power of a mobile device

increases, its power consumption is also increasing.

Since mobile devices are battery-operated, energy efficiency

is the first class constraint for microprocessors.

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WCED'02 The KIT COSMOS Processor 5

Active power of CMOS circuit

Pactive = f × Cload × Vdd2

f：

clock frequency

Cload：

load capacitance

Vdd：

supply voltage

Supply voltage reduction is the most effective

way to lower power consumption.

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WCED'02 The KIT COSMOS Processor 6

Gate delay of CMOS circuit

  • Vdd: supply voltage

Vth: threshold voltage of device α: factor depending upon carrier velocity

saturation

Supply voltage reduction increases gate delay,

which results in slower clock frequency.

Vdd (Vdd-Vth)α Tpd ∝

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WCED'02 The KIT COSMOS Processor 7

Device & circuit optimizations

We can exploit critical path information

Critical path (CP) is the path which decides

processor cycle time (frequency).

Small transistors (tr) on non-CP Low supply voltage for tr.s on non-CP Large threshold tr.s on non-CP Background

Multiple supply voltages (on-chip supplies) Multiple-threshold CMOS, Variable-threshold CMOS

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WCED'02 The KIT COSMOS Processor 8

Architectural-level techniques

We can select functional units based

  • n each instruction’s criticality.

High-speed and power-hungry units

  • eg. CSA, CLA

Low-speed and power-efficient units

  • eg. RCA

Criticality-based instruction scheduling

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WCED'02 The KIT COSMOS Processor 9

Criticality-based scheduling

Dispatch policy is based on each

instruction’s criticality.

Only instructions on critical paths should

be dispatched into fast functional units.

Non-critical instructions can use slow

functional units.

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WCED'02 The KIT COSMOS Processor 10

Critical path

Chain of instructions, which determines

the number of cycles executing program.

I0 I2 I4 I5 I6 I8 I7 I9 I3 I1 I9 I0 I2 I6 I8 I5 Critical path

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WCED'02 The KIT COSMOS Processor 11

Critical path prediction

Tune’s critical path prediction buffer

[HPCA’01]

Simple but uses only local information

Fields’s token passing CP predictor

[ISCA’01]

More accurate due to use of global

information, but complex

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WCED'02 The KIT COSMOS Processor 12

Tune’s CPP buffer

PC Counter critical/not > Th?

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Criticality-based scheduling

Fast and power-hungry

Critical Non-critical Instruction

Slow and power-efficient

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Evaluation

OOO 8-way superscalar processor Based on SimpleScalar/Alpha tool set 6 integer units (fast / slow) 4K-entry CPP buffer, 3-bit counters

+ 1 if critical, -1 if not. Threshold = 5.

SPEC2000 benchmark

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Processor models

Baseline model Power-efficient model

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Vdd and frequency scaling

500MHz 1.0GHz Frequency 1.15V 1.6V Vdd Slow units Fast units

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%Increase in cycles

5 1 1 5 2 2 5 p a r s e r e

  • n

v

  • r

t e x b z i p 2 p i p e l i n e d 3 f a s t / 3 s l

  • w

/ 4 K 5 1 1 5 2 2 5 p a r s e r e

  • n

v

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t e x b z i p 2 n

  • n
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i p e l i n e d 3 f a s t / 3 s l

  • w

/ 4 K

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WCED'02 The KIT COSMOS Processor 18

%Distribution of dispatch

% 2 % 4 % 6 % 8 % 1 % p a r s e r e

  • n

v

  • r

t e x b z i p 2 p i p e l i n e d N S C S N F C F % 2 % 4 % 6 % 8 % 1 % p a r s e r e

  • n

v

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t e x b z i p 2 n

  • n
  • p

i p e l i n e d N S C S N F C F

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WCED'02 The KIT COSMOS Processor 19

%Energy reduction in FU

5 1 1 5 2 2 5 3 3 5 4 4 5 p a r s e r e

  • n

v

  • r

t e x b z i p 2 p i p e l i n e d n

  • n
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i p e l i n e d 5 1 1 5 2 2 5 3 3 5 4 4 5 p a r s e r e

  • n

v

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t e x b z i p 2 p i p e l i n e d n

  • n
  • p

i p e l i n e d

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WCED'02 The KIT COSMOS Processor 20

Clustered microarchitecture

To further reduce power, we split the

instruction queue into a fast and a slow queues.

Fast cluster consists of the fast queue and

fast functional units.

Slow cluster consists of the slow queue and

slow functional units.

2 clusters are connected by small FIFOs,

if necessary.

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Clustered datapath

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Inter-cluster bypassing

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Evaluation

16-entry fast and 48-entry slow queues Every dispatched instructions do not

release its corresponding entry, just like RUU.

36.3% power reduction in the queues.

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Processor models

Non-clustered model Clustered model

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%Increase in cycles

1 2 3 4 5 6 7 8 p a r s e r e

  • n

v

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t e x b z i p 2 p i p e l i n e d 1 6 f a s t Q / 4 8 s l

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Q 1 2 3 4 5 6 7 8 p a r s e r e

  • n

v

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t e x b z i p 2 n

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i p e l i n e d 1 6 f a s t Q / 4 8 s l

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Q

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%Distribution of dispatch

% 2 % 4 % 6 % 8 % 1 % p a r s e r e

  • n

v

  • r

t e x b z i p 2 p i p e l i n e d N S C F % 2 % 4 % 6 % 8 % 1 % p a r s e r e

  • n

v

  • r

t e x b z i p 2 n

  • n
  • p

i p e l i n e d N S C F

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%Energy reduction in FU

  • 4
  • 3
  • 2
  • 1

1 2 3 p a r s e r e

  • n

v

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t e x b z i p 2 p i p e l i n e d n

  • n
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i p e l i n e d

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WCED'02 The KIT COSMOS Processor 28

Summary

Tradeoff between power and performance

can be carefully investigated by exploiting critical path information in architectural-level design as well as device and circuit design.

We evaluated a criticality-based scheduling. It

reduces energy in FUs by over 30%.

We also evaluated a clustered micro-

  • architecture. Currently, it is not always a

good design choice for energy reduction.