Fachgebiet Rechnersysteme Verification Technology Technische Universität Darmstadt
- 6. Model-Checking
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- 6. Model Checking
Fachgebiet RechnerSysteme Verification Technology
Content
6.1 Temporal logic 6.2 CTL 6.3 Symbolic model-checking 6.4 Specification of temporal properties in CTL 6.5 Non-deterministic systems y 6.6 Fairness conditions 6.7 Property specification by automata 6.8 LTL and CTL
- 6. Model-Checking
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What is model-checking? Checking of temporal properties of sequential circuits
Examples: p „It is never possible that all traffic lights are green“ „Eventually, each traffic light will become green“ Model Temporal property Sequential circuit Model- Checker Y N counter example
- 6. Model-Checking
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"It is possible that a=1, b=1, c=1 and d=1 at the same time"
Note: it is much easier to specify this
a b b
+ 5 + 5 + 5 + 5 +1
p y property and do model-checking, rather than to invent input sequences that may lead to this state
c c d d 1
+ + + +
- 1
- a
b c d
represents all reachable states
- 6. Model-Checking
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