Formal verification of low-level execution platforms Apps OS - - PowerPoint PPT Presentation

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Formal verification of low-level execution platforms Apps OS - - PowerPoint PPT Presentation

Dec 21, 2022 215 likes •852 views

Roberto Guanciale Estonian Winter School Day 02 Formal verification of low-level execution platforms Apps OS Hardware Host 1 Motivations Apps Crypto Service OS Hypervisor/ Separation Kernel Hardware Host 1 Motivations Separation

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Formal verification

  • f low-level

execution platforms

Roberto Guanciale Estonian Winter School Day 02

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Motivations

Host 1

Hardware OS Apps

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Motivations

Host 1

Hardware OS Apps Hypervisor/ Separation Kernel Crypto Service

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Hosting untrusted SW (hypervisors host operating systems)

Hosting trusted critical SW

Supporting

CPU sharing

Spatial isolation

Context switch

Communications

Separation Kernel / Hypervisor

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  • Registers (Program Counter)
  • Flags
  • Fetches instruction from memory
  • Executes arithmetical instructions
  • Loads/Stores data from/to memory
  • Has several mode of operations (PL0/PL1)
  • Multiplexed

5 minute course on computer architecture (ARMv7)

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  • Contains instructions
  • Contains data (heap/stack/etc)
  • Is a big table from physical addresses

to bytes

  • Partitioned

5 minute course on computer architecture

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  • Translates virtual addresses to

physical addresses

  • Configured via page tables (stored in

memory) and coprocessors

  • for every va
  • corresponding pa (if mapped)
  • access rights (rd/wt)
  • required mode
  • Enforce access policies

5 minute course on computer architecture

MMU

Load/Store VA Page Tables Load/Store PA Exceptions

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5 minute course on computer architecture

MMU

Load/Store VA Page Tables Load/Store PA Exceptions

  • From PL1 to PL0
  • Special instruction
  • Jump to an arbitrary address
  • From PL0 to PL1
  • Exceptions / Instruction to raise a SW interrupt
  • jump to a fixed address (exception handler)
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ISA model

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ISA model

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Hardware OS Hypervisor Crypto Service

Cooperative scheduling Static memory allocation Message passing Paravirtualization No preemption

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Hardware OS Hypervisor Crypto Service

Cooperative scheduling Static memory allocation Message passing Paravirtualization No preemption

  • executed in PL1
  • invoked via SW interrupt
  • supervises page tables
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A trace of the system

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A trace of the system

Context switch: page tables are updated blue-registers are stored red-registers are loaded

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Security property

  • Non-interference
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Security property

  • Non-interference
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Security property

  • Non-interference
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Security property

  • Non-interference
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Security property

  • Non-interference
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Security property

  • Non-interference

Does not work: the two partitions communicate!

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Top Level Specification

Host 1

Hardware Software Crypto Service

Host 2

Hardware

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Top level specification (ideal world)

  • Two physically separated machine
  • Only one machine active
  • No PL1 computation
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Top level specification (ideal world)

  • Two physically separated machine
  • Only one machine active
  • No PL1 computation

?

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Top level specification (ideal world)

  • Two physically separated machine
  • Only one machine active
  • No PL1 computation

Ideal Functionality

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Top level specification (ideal world)

  • Two physically separated machine
  • Only one machine active
  • No PL1 computation (replaced by atomic functionalities)

Ideal Functionality

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Top level specification (ideal world)

  • Two physically machines (one active)

and hypervisor data

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Top level specification (ideal world)

  • Two physically machines (one active)

and hypervisor data

  • Standard computations

have standard effects

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Top level specification (ideal world)

  • Two physically machines (one active)

and hypervisor data

  • Standard computations

have standard effects

  • Exceptions activate the

ideal functionalities

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Verification Strategy

  • Trace equivalence
  • Unwinding condition based on bisimulation
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Verification Strategy

  • Bisimulation
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Verification Strategy

  • Bisimulation

Weak transitions

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Bisimulation

Reg OS1 Hypervisor OS2 Reg OS1 Reg OS2 h

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Exercise

  • Assuming non-interference property of H: H only depends
  • n the active machine
  • n the content of the memory of other machine at address

OUT2 (OUT1)

  • Assuming non-interference property for guest 2: region of memory

in MEM2 that includes OUT2 does not depend on the content of region K2

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Proof Decomposition: PL0 transitions

  • Non-interference for ARMv7
  • Non dependent by the kernel code
  • Non dependent by the partition code
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Proof Decomposition: PL1 transitions

  • Functional correctness
  • The handlers code respects the specification
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PL0 proof

  • Non dependent by the kernel code / guest code
  • have to be done for every possible instruction
  • Strategy
  • prove SW independent theorems assuming properties of the

system

  • verify that our SW meets this assumptions
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PL0 proof: ISA integrity

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PL0 proof: ISA integrity

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PL0 proof: ISA integrity

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PL0 proof: ISA integrity

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Exercise

  • When is an equivalence relation?
  • Reflexive
  • Symmetric
  • Transitive
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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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PL0 proof: ISA confidentiality

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Proof obligation (O1): page tables

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PL0 Proof: memory equality

  • If machine 1 is active then machine 2 is unchanged
  • from O1 and T1 we know that in the real machine the memory

MEM2 is unchanged

  • thus the equivalence between the real machine and machine 2 for

MEM2 is preserved

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PL0 Proof: memory equality

  • from O1 and T2 we know that the behavior of both the real machine

and machine 1 depends only on memory in MEM1

  • thus the equivalence between the real machine and machine 1 for

MEM1 is preserved

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Proof obligation (O2): page tables

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PL0 Proof: invariants and hypervisor data-structures

  • from definition of TLS we know that the hypervisor data can not be

changed

  • from O2 and T1 we know that in the real machine the memory that

holds these structure can not be changed

  • from O2 and T1 we know that the invariants are preserved
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Exercise

  • Extend the model and proofs to handle a Memory Mapped device

(UART)

  • Address DevOut can be used to write something
  • Address DevIn can be used to read something
  • Device fetches and writes into these addresses
  • Partition 2 should be in control of the device
  • Device transitions are interleaved with CPU transitions (assume

the device does not perform any action while the CPU is in PL1)

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Exercise

  • How should DMA devices be handled?
  • Address DevOut can be used to write a pointer
  • Address DevIn can be used to write a pointer
  • Device fetches these pointers and writes/reads into the pointed

memory

  • Partition 2 should be in control of the device
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Exercise

  • Extend the toy CPU with a new instruction
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Summary

  • ISA model
  • Verification Goal (via TLS)
  • Proof decomposition
  • Sketch of proof for PL0
  • Upcoming
  • Verification for PL1
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THANKS! Any questions?

You can find me at robertog@kth.se http://prosper.sics.se/

References