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Fr Front t End Bo Board Requirements, Speci cification and QA/ QA/QC QC Alexander Singovski, L4 FE manager PreFinal Design Review Dec. 12-14, 2018 Alexander Singovski ECAL FE board NSF Pre-FDR

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 1

Fr Front t End Bo Board Requirements, Speci cification and QA/ QA/QC QC

Alexander Singovski, L4 FE manager PreFinal Design Review

  • Dec. 12-14, 2018
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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 2

§Manager and engineering team bio § Requirements and specifications § Interface control § Design and Prototyping § QA/QC plan

Outline

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 3

Project Manager

Alxander Singovski § Education: Moscow Institute of Physics and Technology, PhD on experimental particle physics, IHEP Protvino, Russia § Current position: Physicist, University of Notre Dame § Relevant experience

  • Deputy Spokesman of WA102 experiment at CERN (Glueball search

at CERN Omega facility)

  • Responsible for the hardware and data analysis software of the lead-glass

electromagnetic calorimeter

  • CMS ECAL Optical Links and Low Voltage projects coordinator
  • Design, production and testing of the CMS ECAL on-detector data transmission

and control units: Giga Opto-Hybrids (GOH) and Token Ring Link boards

  • CMS ECAL Beam Tests coordinator
  • CMS ECAL Upgrade coordinator 2010-2014
  • Fundamental study of the CMS ECAL component longevity and radiation

tolerance

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 4

Engineering Team

Nikitas Loukas Current position: Electronic Engineer, University of Notre Dame Professional qualification: PhD in electronic engineering, University of Ioannina, Greece Relevant experience:

  • CMS member for 6 years.
  • Barrel muon trigger development.
  • Responsible for the ECAL Barrel Calorimeter Processor (BCP) design

Alexander Dolgopolov Current Position: Electronic Engineer, University of Notre Dame Professional qualification: Moscow State University of Instrument Engineering and Computer Science Relevant experience:

  • ADC system COMPASS experiment at CERN
  • Design and tests of GOL opto-hybrids, ECAL FE card
  • Design and tests of ECAL on-detector Token Ring boards
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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 5

§ Should serve one Trigger tower: 5x5 crystals, 5 VFE boards § Should fit to the legacy FE card dimensions § Should fit to the HL-LHC radiation environment

§

1 Mrad

§

104 n/cm2

§ Should stream the data generated by five VFE boards off-detector with no loss

§

Total data rate ~40Gb/s

§ Should deliver high precision (<10ps jitter) clock to VFE components § Should provide data flow synchronization: transmit synch. Commands from off-detector to VFE with the fixed latency § Should provide slow control functions required by VFE and LVR boards

§

configuration registers setting (I2C interface)

§

Power voltage monitoring

§

Temperature monitoring

Requirements & specifications

BCAL-sci-engr-001 BCAL-sci-engr-002 BCAL-sci-engr-004 BCAL-engr-040 BCAL-engr-010 BCAL-engr-001 BCAL-engr-008

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 6

Scope of the project

Per crystal:

  • Pre-amp 3 ranges
  • 12 bit ADC
  • 14 bit data @ 40 MHz
  • 560 Mbps data flow

Per VFE card:

  • 5 crystals
  • 2.8Gbps @

40 MHz sampling Per Trigger Tower:

  • 5 VFE cards
  • 14Gbps @ 40 MHz
  • à 0.8Gbps TRIGGER

primitives

  • L1 trigger à 0.8Gbps

DATA

Optical transmitters 2x 0.8Gbps (GOL) Level 1 trigger

Data rates:

Per VFE card:

  • 5 crystals
  • 10.4Gbps @ 160 MHz
  • 5.4Gbps @ 160Mhz @

compression Per Trigger Tower:

  • 5 VFE cards
  • 52Gbps @ 160 MHz
  • 27Gbps @ 160Mhz @

compression

Level 1 trigger

ECAL Upgrade on-detector electronics ECAL legacy on-detector electronics

Optical transmitters 8x4.8Gbps (GBTx)

  • r

4x 10.24Gbps (lpGBT)

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 7

FE Interfaces

§

7 I2C Masters

§

25 +3 clock lines all from Master lpGBT

§

25 control down e-links, one per LiTe-DTU

§

20 Power voltage monitoring: 2 per VFE, 7 LVR

§

30 thermal sensors

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 8

Interface Control

§

7 I2C Masters

§

25 +3 clock lines all from Master lpGBT

§

25 control down e-links, one per LiTe-DTU

§

20 Power voltage monitoring: 2 per VFE, 7 LVR

§

30 thermal sensors

Upgrade FE card project Resp: A.Singovski, University of Notre Dame Upgrade Barrel Calorimeter Processor project Resp: N.Loukas University of Notre Dame Upgrade VFE card project Resp: W.Lusterman ETH, Zurich Upgrade LVR card project Resp: W.Lusterman ETH, Zurich

  • All L4 Projects managers are CERN-based
  • Regular project discussions at the ECAL Upgrade

meetings

  • Close personal contacts
  • Documentation storage at the CERN EDMS
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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 9

Upgrade FE card design

§

Legacy ECAL FE card dimensions

§

4 lpGBT chips

§

One 4T1Rx Versatile_Link+ hybrid

§

Enough surface to place 7 lpGBT and 2 4T1R, plus

  • ptional DC-DC converter,

plus optional GBT

  • SCA

§

Comfortable tracing for baseline option: 4 lpGBT & 1 4T1Rx

§

Major challenge – 4-7 e-links @ 320Mbps per DTU è 100 - 175 total

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 10

GBT (2010-2015)

§ Dedicated chipset for the high speed data transmission, compatible with HL-LHC environment § Efficient error correction protocol § Bandwidth 5 Gb/s

§

User data rate 3.36Gb/s

§ Radiation tolerance

§

Gamma – 100 Mrad

§

Neutrons 105 n/cm2

§ Available in big quantities. Mass production ended in 2015

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 11

lpGBT

What’s the lpGBT? lpGBT project schedule

Components description available for

  • users. Start of

the Prototype2 design Limited number of chips for users. Pritotype2 production

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 12

Prototyping Schedule

§ Prototype 0: “FE demonstrator”, Q4 2017

  • 1 VTRx & 1 VTTx VL module,
  • Can receive data from 5 legacy VFE (one VFE-FE data channel fully functional, one – partially)
  • Used during 2017-2018 beam tests to get spikes data sample (analysis on-going)

§ Prototype 1 “smart” GBTx – based EF card, Q2 2018

  • 1 VTRx & 2VTTx VL modules,
  • Will receive data from 5 legacy or upgrade VFE
  • Clock to VFE from one source
  • I2C via optical down-link

§ Prototype 2: Realistic lpGBT – based FE card Q4 2019

  • V4T1Rx+ VL+ optical module
  • Optimal clock to VFE distribution
  • Both lpGBT chain and GBT-SCA control options
  • Both multi-node down e-link and 1-to-5 fanout

§ Prototype 3: final configuration Q1 2020

  • V4T1Rx+ VL+ optical module
  • Optimal clock to VFE distribution
  • Final control design
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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 13

Demo Board(2017)

Readout via mTCA backend prototype

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 14

§ First experience with the CERN custom fast data link components: GBTx chipset and Versatile Link hybrids § Implementation of the specific clock distribution for the high speed serial links § Definition of the initialization and configuration sequence § Definition of the required PCB and assembly quality § Beam tests: data transfer from the legacy VFE to the mTCA upgrade off-detector units prototypes § Definition of the Prototype1 design

Demo board outcome

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 15

Prototype Board V1 (2018)

Ref clk IN e-link clk OUT GBTx configuration I2C GBTx master I2C GBTx slaves I2C GBT-SCA GBTx GBT- SCA VL TTx

§ Several options for system clock to Slave GBTx, including recovered and e-link clock from Master GBTx § E-link clock to VFE from Master GBTx § Configurable interface to VFE: e-links @ (80, 160 or 320) Mbps § Electrical and optical I2C § Can be connected to

  • Legacy VFE via Adapter card
  • Upgrade VFE either directly or via

Adapter card § Max data rate: 5x3.36=16.8Gbps § Can transmit data from:

  • 5 legacy VFE @ 40Mhz clock
  • 1 DTU per Upgrade VFE @ 160MHz clock

without Adapter

  • 5 Upgrade VFE @ 160MHz with buffer in

Adapter § Can be powered either from Upgrade LVR card

  • r from external power supply

Power

input

VL TTx VL TRx GBTx GBTx GBTx GBTx VFE connectors

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 16

Prototype 1: up-links

Data transmission @ 5Gb/s Recovered clock from Master GTBx Eye diagrams looks good. Stable data transmission.

GBTx phase locking mechanism is working well

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 17

Prototype 1: precision clock to VFE

Clock to VFE Main conclusion: in GBTx the clock path from master input to s-link recovered introduce jitter at <10ps level à good enough for the final system specs. 40 MHz 160 MHz

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 18

§ Fully functional FE card, meet specifications § Fast data links

§ Up-links: optical @ 5Gb/s, electrical @

320Mb/s

§ Down-links: optical @ 5Gb/s, electrical @

80Mb/s § Realistic configuration sequence: Master à Slaves à VFE components § Data link and clock quality measurements § Definition of the lpGBT – based Prototype2 design

Prototype1 outcome

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 19

Prototype board V2 (2019)

v Prototype 2

§ 4 x lpGBT based § Versatile_Link+ hybrid: 1 x 4T1Rx § UP e-links @ 320, 640 , and 1280 Mb/s § Electrical & optical I2C. Separate for Master and Slave chips § Clock to VFE: recovered e-link clocks from Master lpGBT § Clock to Slave lpGBT – on-board switch select: external or recovered from Master § 5 x down e-links @ 160 Mb/s

v Can be tested:

§ Up-links

§ Optical @ 10 Gb/s § E-links @ 320 and 1280 Mb/s

§ Clock quality § Slave GBTx configuration

ü via optical down-link: Master lpGBTx – I2C master-slave chain – Slave GBTx ü via GBT-SCA

§ Data synchronization via e-links

ü VFE simulator with lpGBT (if many lpGBT chips available) ü VFE with ADC-LiteDTU

§ Radiation tolerance

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 20

Prototype 2 layout

VL+ 4T1R lpGBT lpGBT lpGBT lpGBT

Sketch of the possible Prototype 2 layout

§

Prototype1 PCB

§

ECAL FE card dimensions

§

Standard 4T1Rx Versatile_Link+ hybrid

§

lpGBT footprint scaled from GBTx

§

Comfortable tracing for baseline option: 4 lpGBT & 1 4T1Rx

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 21

Components radiation and B-field tolerance

  • All GBT and VL+ components will be certified to CMS Tracker radiation

level

  • 10 times more severe than ECAL requirements
  • Fully assembled Prototype 2 board will be certified by ECAL group: full

functionality test at:

  • Neutron irradiation to 10 14 neutrons /cm2
  • Gamma irradiation 10KGy
  • Proton/Pion irradiation to 10 13 particles/cm 2
  • Climatic chamber for ageing. 5 cycles: 1 week @ 80C each, full test between

cycles.

  • 2-4 Tl magnetic field
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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 22

§ Prototype2 will allow to choose between two

  • ptions for the fast and high precision clock and

control FE à VFE connection:

§ Clock:

§ Direct distribution via lpGBT clock manager § Parallel high precision clock chain

§ Control:

§ E-link with 5 nodes on VFE, connected in parallel § Single node E-links with fanout on VFE card

§ After selection of the optimal clock and control distribution, the final fully optimized Prototype3 will be produced.

Proto 3/preprod

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 23

FE production plans

§ Preproduction series

2020

  • 100 FE cards produced
  • Sufficient for one Super Module

§ Full functional test, SM37

2020-2021

  • Spare Super Module 37 equipped with upgrade on-detector

electronics

  • Power and thermal tests in the lab
  • Beam test at CERN

§ Longevity test 2021

  • 100 FE cards in climatic chamber: accelerated ageing at 90C,

thermal cycling. Functional test between cycles

§ Production readiness review Q1 2021 § Production 2022-2022 Require dedicated test stand for the full functional test of ALL production units

One year ahead of the ECAL electronics replacement which starts it 2023

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 24

§ Production quantity: total 2516 FE boards installed, plus 10% spares à 2800 boards § Production by 4 batches, 700 units each. Next batch after the previous batch acceptance test § Quality test by producer

§ Visual inspection in ~100 points § Passive power lines test: resistance § Power ON/OFF

§ Full qualification at CERN. (QA/QC document attached to the

agenda)

§ All units in the climatic chamber: 4 days @80C § Full functional test at CERN § Boards delivered to ECAL TC (Integration center)

Production

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 25

§ Prototype1 (GBTx chipset)

§ Evaluation of the required PCB and assembly precision § Tag possible board producers § Investigation of the influence of the design details on the key performance

features like clock and data transmission quality

§ Prototype2 (lpGBT chipset + optional GBT-SCA)

§ Validation of the design solutions § Detailed performance evaluation § Radiation and magnetic field tolerance

§ Prototype3 (lpGBT chipset)

§ Final design evaluation

§ Pre-production

§ Large number of boards § Evaluation of the production quality § Evaluation of the radiation tolerance § Evaluation of the longevity

QA/QC steps

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 26

§ ECAL Front End (FE) card upgrade project is on schedule § Detailed specification is under configuration control

§ Working document § Under development, depend on the components specs, which are

not all available so far

§ Linked to the VFE and BCP specs

§ Interface control in place. Interface managers defined § Production and QA/QC plan developed

Summary

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 27

Backup slides

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 28

FE test stand

Mother board which contain

  • Connectors. Board should contain a full set of input and output connectors of the FE card, plus

service connectors for tests and e-fuses burning

§ VFE – type connectors, full Tower à 5 VFEs § LVR connector § Optical MT or MFS with MT-MFS adapter § Electrical i2C with 3V option for e-fuse burning

  • Processor. FPGA with sufficient power to provide:

§ Full simulation of five VFE cards: data generation, I2C interfaces, clock and control functions, voltage and temperature monitoring § Clock quality testing: pulse shape, jitter, stability. § Optical up-link simulation: GBT protocol, optical clock generation, control functions

Power connection: simulation of LVR card

§ LV for FE functioning § LV for e-fuse burning § Initialization and control functions

Test stand should allow a full automatic functional test of the FE card, including data transfer, clock quality evaluation, eye-diagrams for the optical up-links. Preferably based on the same FPGA as one used in BCP to simplify the firmware development.

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 29

Legacy FE test stand

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Alexander Singovski ECAL FE board NSF Pre-FDR Assessment Dec. 12-14, 2018 p. 30