Hardware Acceleration of Database Operations Jared Casper and Kunle - - PowerPoint PPT Presentation
Hardware Acceleration of Database Operations Jared Casper and Kunle Olukotun Pervasive Parallelism Laboratory Stanford University Database machines n Database machines from late 1970s n Put some compute on the disk track/head/unit n
n Put some compute on the disk track/head/unit n Processors got faster, I/O performance did not n Processor could keep up with disk
n No performance left on the table
n Made up of general purpose components n Massive amounts of memory n Very high speed interconnect n Tables, even databases, fit entirely within memory
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n Join performance is at 100s of million tuples per
n 64-bit tuples → 2-3 GB/s n Chips can get over 100 GB/s n Performance is being left on the table
n Selection, merge join, sort n Combine these to do a sort merge join n Goal is to “keep up with memory”
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n Read data into SIMD register n Use SIMD shuffle operation to move selected data to
n Mask used as index into table for shuffle values
n Unaligned write to append to output n Limited by SIMD width, number of SIMD registers
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1 0 1 1 1 0 0 1 C F E B E C A F E B A B E
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n Can have associated values or record IDs n Output cross product when multiple values n Generally viewed as the “free” thing after sorting
n More an indication of how slow sorting is
n Limits the IPC → hard to keep up with memory
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7 ¨ Output is bitmask of equal keys with corresponding values
¤ Ready for input into the select block
8 4 8 2 1 5 5 7 4 8 1 2 5 5 0 7 1 2 4 8 0 5 5 7 0 1 2 4 5 5 7
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¨ Sort, merge join, and select blocks are combined to
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n STREAM achieved 12 GB/s (57%)
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10 20 30 40 50 60 70 80 90 100
Cardinality (%)
16 17 18 19 20 21 22 23 24
Throughput (GB/s)
42 44 46 48 50 52 54 56 58 60 62 64
% of Line Bandwidth
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64 88 112 136 160 184 208 232 256 280 304 328 352 376
Throughput (bytes/clock)
24 36 48 60 72 84 96 108 120 132
Throughput (GB/s @ 400 MHz)
2 4 6 8 10
Count (thousands)
ROM bits 16:1 mux 4:1 mux registers
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¨ Resources required is a quadratic function of desired bandwidth
¤ All in comparison logic, routing was the limiting factor
¨ Above 1.5x output, write bandwidth dominates
¤ Throughput above is input consumed
0.15 0.3 0.45 0.6 0.75 0.9 1.05 1.2 1.35 1.5
Output ratio
8 10 12 14 16
Throughput (GB/s)
18 20 22 24 26 28 30 32 34 36
% T
m=1 m=2 m=3 m=8
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¨ Resources required is a linear function of desired input size ¤ Dominated by the memory required to hold working sets ¨ Recent CPU/GPU numbers ~300M 32-bit values per second
375K 750K 1.5M 3M 6M 12.5M 25M 50M 100M 200M 400M 800M 1.6B 3.2B 6.4B 12.5B 25B 50B
Size of Input
400 600 800 1000 1200 1400 1600
Million values per second
2 passes 3 passes 3 passes (projected)
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n Performance limited by intra-FPGA link n Total throughput is 800 million tuples/second
n ~6.5 GB/s n 8x previous work on software joins
n Make the most of every byte read n In some cases, address bandwidth is just as important
n Think streaming
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