INF5140 – Specification and Verification of Parallel Systems
Lecture 5 - Introduction to Logical Model Checking and Theoretical Foundations Spring 2015
Institutt for informatikk, Universitetet i Oslo
April 20, 2015
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INF5140 Specification and Verification of Parallel Systems Lecture - - PowerPoint PPT Presentation
INF5140 Specification and Verification of Parallel Systems Lecture 5 - Introduction to Logical Model Checking and Theoretical Foundations Spring 2015 Institutt for informatikk, Universitetet i Oslo April 20, 2015 46 / 108 Credits
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all possible executions all invalid executions
executions that are possible and invalid 53 / 108
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1950 2004 1975 1968 1989 1980 1995 2000 1936
C C++ 1976-1979: first experiments with reachability analyzers (e.g., Jan Hajek: ‘Approver’) 1981: Ed Clarke and Allen Emerson introduce the term ‘model checking’ and the logic CTL* 1980: earliest predecessor
1993: BDDs and the SMV model checker (Ken McMillan, CMU) 1989: Spin version 0 verification of class of
1995: partial order reduction in Spin. LTL conversion in Spin. (Doron Peled) Spin SMV
the two most popular logic model checking systems today: Spin: an explicit state LTL model checker based on automata theoretic verification method targeting software verification (asynchronous systems) SMV: a symbolic CTL model checker targeting hardware circuit verification (synchronous systems) (there are hundreds of other model checkers – there are also several variants of Spin)
1986: Pierre Wolper and Moshe Vardi define the automata theoretic framework for LTL model checking 1986: Mazurkiewicz paper on trace theory 1977: Amir Pnueli introduces linear temporal logic for system verification LTL CTL 2001: support for embedded C code in Spin version 4.0 Spin 4.0 1968: two terms introduced: software crisis software engineering 1960: early work on
e.g., by J.R. Buchi 2003: breadth-first search mode added in Spin version 4.1 Fortran Algol 1975: Edsger Dijkstra’s paper
1978: Tony Hoare’s paper on Communicating Sequential Processes 1940-50: the first computers are built 1955: early work on tense logics (predecessors of LTL) 1936: first theory on computability, e.g., Turing machines
key theoretical developments underlying Spin
pan
C
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after-you, no after-you blocking me-first, no me-first blocking
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int x, y, r; int *p, *q, *z; int **a; thread_1(void) /* initialize p, q, and r */ { p = &x; q = &y; z = &r; } thread_2(void) /* swap contents of x and y */ { r = *p; *p = *q; *q = r; } thread_3(void) /* access z via a and p */ { a = &p; *a = z; **a = 12; }
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9! 6! 3!
6!.3! 3!.3! 3!
placing 3 sets of 3 tokens in 9 slots
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2 2 2
4 4 4
5 5 5
1 1 1
3 3 3
0, α
1 1 1, α
2 2 2, α
3 3 3, α
4 4 4, α
5 5 5 }
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2 2 2
4 4 4
5 5 5
1 1 1
3 3 3 66 / 108
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idle ready execute
end
waiting start pre-empt run block unblock stop
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idle ready execute
end
waiting start pre-empt run block unblock stop
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idle ready execute
end
waiting start pre-empt run block unblock stop
{ start, run, { { pre-empt, run } + { block, unblock } }*, stop }
a characterization of the complete language of automaton A (an infinite set of words): the shortest word in the language: { start, run, stop } a regular expression +: choose *: repeat zero
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interpretation:
p q !r r !p !q error
correctness claim: it is an error if in a run we see first p then q and then r
this property is easily expressed with the standard definition of acceptance reaching this state constitutes a complete match of the pattern that specifies the correctness violation 72 / 108
Problem: we cannot express this with the standard definition of acceptance: we cannot express that a run may not remain in the error state infinitely long...
p !q !p error
attempted interpretation:
q
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execute end
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true p (ltl2ba -f) p !p true !p 85 / 108
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n
1Alternatively, the property can be given directly as a Büchi automaton 88 / 108
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s0 s1 (x%2) x=3x+1 A1 s0 s1 !(x%2) x=x/2 A2 s0 s1 true x<4 x<4 B s0,s0 s1,s0 s0,s1 s1,s1 (x%2) x=3x+1 (x%2) x=3x+1 x=x/2 x=x/2 !(x%2) !(x%2)
Π Π Π Π
an unreachable state under Promela interpretation
int x
note that variable x also holds state information we have to take Promela semantics into account to determine which states are really reachable
we can also “expand” the automaton into a pure automaton, without variables
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s0,s0 s1,s0 s0,s1 s1,s1 (x%2) x=3x+1 (x%2) x=3x+1 x=x/2 x=x/2 !(x%2) !(x%2) s0,s0 4 s0,s1 4 s0,s0 2 s0,s1 2 s1,s0 1 s0,s0 1 !(x%2) x=x/2 !(x%2) x=x/2 (x%2) x=3x+1 “pure” finite state asynchronous product automaton for initial value x = 4 (the value of x is now part of the state of the automaton)
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s0 s1 true x<4 x<4 B all paths with accept states dead-end here; not stutter possible are there any accepting cycles? if not, then the property <>[](x<4) cannot be satisfied and its negation holds !<>[](x<4) [] []<>!(x<4) []<>(x>=4)
s0,s0, 4,s0 s0,s1 4,s0 s0,s0 2,s0 s0,s1 2,s0 s1,s0 1,s0 s0,s0 1,s0 !(x%2) x=x/2 !(x%2) x=x/2 (x%2) x=3x+1 x=x/2 (x%2) s1,s0 1,s1 s0,s0 1,s1 s0,s1 2,s1 s0,s0 4,s1 s0,s0 4 s0,s1 4 s0,s0 2 s0,s1 2 s1,s0 1 s0,s0 1 !(x%2) x=x/2 !(x%2) x=x/2 (x%2) x=3x+1 i=1 2
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2 , where σ1
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2 is a counterexample that is accepted by
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[Büchi, 1960] Büchi, J. R. (1960). Weak second-order arithmentic and finite automata. Zeitschrift für mathematische Logik und Grundlagen der Mathematik, 6:66–92. [Büchi, 1962] Büchi, J. R. (1962). On a decision method in restricted second-order logic. In Proceedings of the 1960 Congress on Logic, Methodology and Philosophy of Science. Stanford University Press. [Holzmann, 2003] Holzmann, G. J. (2003). The Spin Model Checker. Addison-Wesley. [Manna and Pnueli, 1992] Manna, Z. and Pnueli, A. (1992). The temporal logic of reactive and concurrent systems—Specification. Springer-Verlag, New York. [Peled, 2001] Peled, D. (2001). Software Reliability Methods. Springer-Verlag. 108 / 108