Introduction to SystemC Damien Hubaux - CETIC Supported by the - PDF document

www.cetic.be Introduction to SystemC Damien Hubaux - CETIC Supported by the European Union (ERDF) and the Walloon Region (DGTRE) Outline • Why SystemC? www.cetic.be • What is SystemC? – A language – A C++ library • Why SystemC • Advantages • What is SystemC - Language • Drawbacks - C++ Library • Perspectives • Advantages • Drawbacks • Perspectives Supported by the European Union (ERDF) and the Walloon 2 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

Why SystemC? • Needs www.cetic.be – Increasing complexity, gate number, simulation time, verification effort, hw/sw co-design, etc. • Why SystemC • Context of new languages / tools: • What is SystemC - Language – Verification languages (PSL, sugar, vera), - C++ Library – High-level synthesis (Handel-C, Precision C, • Advantages behavioural synthesis, etc). • Drawbacks • Perspectives • Common C/C++ modeling – Several event-based C/C++-based simulators exist(ed): in-house, Cynlib, SpeC, Ocapi – Common effort, common language -> SystemC – Need for standardisation Supported by the European Union (ERDF) and the Walloon 3 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) Why SystemC? • EDA developers www.cetic.be – Small market (compared to SW) – Base a new language on an existing widely used language • Why SystemC • Rely on existing tools • Focus on EDA specificity • What is SystemC - Language - C++ Library • Common interest from several companies • Advantages – Contributions from existing internal • Drawbacks technologies (Synopsys, CoWare, Adelante Technologies (was: Frontier Design)) • Perspectives – Now extended to others Supported by the European Union (ERDF) and the Walloon 4 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

What is SystemC? • OSCI: Open SystemC Initiative www.cetic.be • OSCI’s Language Reference Manual (LRM) – A Hardware Description language • Why SystemC – A C++ library that implements hardware • What is SystemC concepts (clock, ports, concurrency, etc) - Language - C++ Library • Advantages • The reference implementation of this • Drawbacks language • Perspectives – Reference!!! (one of the possible...) – Open-source, freely available Supported by the European Union (ERDF) and the Walloon 5 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) What is SystemC? • Associated libraries (from OSCI) www.cetic.be – Extension are possible – Master-Slave library: abstract communications – Verification library: offers to SystemC more • Why SystemC verification features (assertion, introspection, etc.) • What is SystemC - Language - C++ Library • Contributions of the OSCI working • Advantages groups • Drawbacks – Language • Perspectives – Transaction Level Modeling – Verification – Synthesis Supported by the European Union (ERDF) and the Walloon 6 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

What is SystemC? • There are (have been) 2 (successive) www.cetic.be "opinions" about SystemC • RTL modeling using C++ • Why SystemC – What is the benefit compared to my favourite • What is SystemC HDL? - Language - C++ Library – (Looks suspect to HW designers) • Advantages • Drawbacks • System level modeling • Perspectives – Between system (C++, Matlab, etc), software, and hardware designers (HDL) • C/C++ is possible • RTL is possible • Everything between • Mixing algorithmic and RTL • Mixing HW and SW Supported by the European Union (ERDF) and the Walloon 7 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) Outline • Why SystemC? www.cetic.be • What is SystemC? – A language – A C++ library • Why SystemC • Advantages • What is SystemC - Language • Drawbacks - C++ Library • Perspectives • Advantages • Drawbacks • Perspectives Supported by the European Union (ERDF) and the Walloon 8 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

A Hardware Description Language • You can write (RTL) SystemC without www.cetic.be really knowing C++ • Let's make a short comparison: VHDL / SystemC • Why SystemC • What is SystemC ENTITY Mouse IS SC_MODULE(Mouse) - Language - C++ Library • Advantages • Drawbacks • Perspectives SC_METHOD(Phone); PROCESS Phone (ring) sensitive<<ring; Supported by the European Union (ERDF) and the Walloon 9 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) Declaration entity my_module is SC_MODULE(my_module) www.cetic.be [ports] { end my_name [ports] [signals] • Why SystemC [modules] architecture my_arch of [processes (decl.)] • What is SystemC - Language my_module is SC_CTOR(my_module){ - C++ Library [components] [processes • Advantages [types] (sensitivity)] • Drawbacks [signals] } • Perspectives begin }; [processes (all)] [combinatorial] end [processes (implementation)] Supported by the European Union (ERDF) and the Walloon 10 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

Entity / Ports entity my_name is SC_MODULE(my_name) www.cetic.be port( { ... [ports] [ports] ); }; • Why SystemC end my_name • What is SystemC - Language - C++ Library • Advantages • Drawbacks port ( { • Perspectives input: port1 std_logic; sc_in<bool> port1; output: port2 std_logic; sc_out<bool> port2; ); ... }; Supported by the European Union (ERDF) and the Walloon 11 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) Hierarchy architecture my_arch #include "child.h" //decl www.cetic.be of my_module is SC_MODULE(my_module) component child { port(...); • Why SystemC child* child_inst; end component; SC_CTOR{ • What is SystemC - Language child_inst = new child; - C++ Library Begin child_inst.in->(signal1); • Advantages child_inst : child ... • Drawbacks port map( } • Perspectives in => signal1; }; ... ); ... Supported by the European Union (ERDF) and the Walloon 12 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

Processes process my_process (clk, void my_process(); www.cetic.be reset) if (reset) SC_CTOR(){ ... SC_METHOD(my_process); elseif(clk'event and • Why SystemC sensitive_pos<<clk; clk=='1') sensitive<<reset; • What is SystemC ... - Language } - C++ Library endif • Advantages • Drawbacks void my_process() • Perspectives { if (reset==1) ...; else ...; end; } Supported by the European Union (ERDF) and the Walloon 13 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) Data types / Assignment • bit www.cetic.be • std_logic • std_logic_vector (X dowto 0) • Enumeration • unsigned (X dowto 0) • Integer • signal my_sig: ...; • Floating-point • Why SystemC • ... • Physical • What is SystemC • Array - Language - C++ Library • bool or sc_bit • Advantages • sc_logic • sc_lv[X] • Drawbacks • sc_uint<X> • Perspectives my_var1 := my_var2; • sc_signal<...> my_sig; my_sig1 <= my_sig2; • ... my_var1 = my_var2; my_sig1 = my_sig2; my_sig1.write(my_sig2); Supported by the European Union (ERDF) and the Walloon 14 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)

Outline • Why SystemC? www.cetic.be • What is SystemC? – A language – A C++ library • Why SystemC • Advantages • What is SystemC - Language • Drawbacks - C++ Library • Perspectives • Advantages • Drawbacks • Perspectives Supported by the European Union (ERDF) and the Walloon 15 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE) A C++ library • Classes that implement hardware data- www.cetic.be types and concepts • A simulation kernel: registering • Why SystemC functions in order to allow "parallel" • What is SystemC execution. - Language - C++ Library • Advantages • Possibility to extend with own data- • Drawbacks types, concepts • Perspectives – Support for own methodology – Support for own libraries – Support all C/C++ you want Supported by the European Union (ERDF) and the Walloon 16 February 12, 2004 SystemC, an alternative for system modeling and synthesis? Region (DGTRE)