Lecture 6: Sequential Networks: Latches and flip flops CSE 140: - - PowerPoint PPT Presentation

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Lecture 6: Sequential Networks: Latches and flip flops CSE 140: - - PowerPoint PPT Presentation

Sep 22, 2023 167 likes •492 views

Lecture 6: Sequential Networks: Latches and flip flops CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1 Flight attendant call button

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SLIDE 1

Lecture 6: Sequential Networks: Latches and flip flops

CSE 140: Components and Design Techniques for Digital Systems

Diba Mirza

  • Dept. of Computer Science and Engineering

University of California, San Diego

1

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SLIDE 2

Flight attendant call button

  • Flight attendant call button

– Press call: light turns on

  • Stays on after button released

– Press cancel: light turns off – Logic gate circuit to implement this?

2

a

Bit Storage Blue light Call button Cancel button

  • 1. Call button pressed – light turns on

Bit Storage Blue light Call button Cancel button

  • 2. Call button released – light stays on

Bit Storage Blue light Call button Cancel button

  • 3. Cancel button pressed – light turns off
  • SR latch implementation

– Call=1 : sets Q to 1 and keeps it at 1 – Cancel=1 : resets Q to 0

R

S

Q

C all button

Blue light

Cancel button

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SLIDE 3

SR (Set/Reset) Latch

R S Q Q N1 N2

  • SR Latch
  • Consider the four possible cases:

§ S = 1, R = 0: set output to ‘1’ § S = 0, R = 1: (reset) output to ‘0’ § S = 0, R = 0: store – output should be unchanged § S = 1, R = 1: Trouble!

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(S+Q)’

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SLIDE 4

SR Latch Analysis

§ S = 1, R = 0: § S = 0, R = 1:

R S Q Q N1 N2 1

R S Q Q N1 N2 1

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SLIDE 5

SR Latch Analysis

§ S = 0, R = 0:

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R S Q Q N1 N2

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SLIDE 6

SR Latch Analysis

§ S = 0, R = 0:

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R S Q Q N1 N2

What happens if Qprev=0 and Q’prev=0?

  • A. The output Q toggles
  • B. The output Q remains 0 and Q’ changes to 1
  • C. The output Q becomes 1 and Q’ remains 0
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SLIDE 7

SR Latch Analysis

– S = 1, R = 1:

R S Q Q N1 N2 1 1

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SLIDE 8

Flip-flop Components

S R

SR latch (Set-Reset)

Inputs: S, R State: (Q, y) y Q

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SR=01, (Q,y) = (0,1) SR=10, (Q,y) = (1,0) SR=11, (Q,y) = (0,0) SR = 00 => if (Q,y) = (0,0) or (1,1), the output keeps toggling

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SLIDE 9

Q: Which of the following is a good solution to avoid the output from toggling? A) Avoid the input SR = (0,0) B) Avoid the input SR = (1,1)

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SLIDE 10

SR Latch Analysis

– S = 0, R = 0: then Q = Qprev and Q = Qprev (memory!) – S = 1, R = 1: then Q = 0 and Q = 0 (invalid state: Q ≠ NOT Q)

R S Q Q N1 N2 1 1

R S Q Q N1 N2 1 1 R S Q Q N1 N2 1 1 Qprev = 0 Qprev = 1

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SLIDE 11

0 0 0 X 1 1 1 0 X 1

PS

inputs

00 01 11 10 State table Q(t+1)

SR Characteristic Expression Q(t+1) = S(t)+R’(t)Q(t)

NS (next state) Q(t)

11

S R Q Q SR Latch Symbol

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SLIDE 12

SR Latch Symbol

  • SR stands for Set/Reset Latch

– Stores one bit of state (Q)

  • Control what value is being stored with S, R inputs

– Set: Make the output 1 (S = 1, R = 0, Q = 1) – Reset: Make the output 0 (S = 0, R = 1, Q = 0)

12

Must do something to avoid invalid state (S = R = 1)

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SLIDE 13

Clocks

13 Sources: TSR, Katz, Boriello, Vahid, Rosing

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SLIDE 14

Clock question

The clock shown in the waveform below has:

  • A. Clock period of 4ns with 250MHz frequency
  • B. Clock duty cycle 75%
  • C. Clock period of 1ns with 1GHz frequency
  • D. A. & B.
  • E. None of the above

14

1ns CLK

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SLIDE 15

D Latch

D Latch Symbol CLK D Q Q

  • Two inputs: CLK, D

– CLK: controls when the output changes – D (the data input): controls what the output changes to

  • Function

– When CLK = 1, D passes through to Q (the latch is transparent) – When CLK = 0, Q holds its previous value (the latch is opaque)

  • Avoids invalid case when Q ≠ NOT Q

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SLIDE 16

D Latch Internal Circuit

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S R Q Q SR Latch Symbol

CLK D S R Q Q’ 1 1 1 1

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SLIDE 17

D Latch Internal Circuit

S R Q Q Q Q D CLK

D R S

CLK D Q Q

S R Q Qprev 1 1 1 Q 1 CLK D X 1 1 1 D X 1 Qprev

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SLIDE 18

D Flip-Flop

  • Two inputs: CLK, D
  • Function

– The flip-flop “samples” D on the rising edge of CLK

  • When CLK rises from 0 to 1, D passes through to Q
  • Otherwise, Q holds its previous value

– Q changes only on the rising edge of CLK

  • A flip-flop is an edge-triggered device because it is activated on the clock edge

(when CLK rises from 0 1) – D passes through to Q

D Flip-Flop Symbols D Q Q

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SLIDE 19

D Flip-Flop Internal Circuit

CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

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  • When CLK = 0

– L1 is transparent, L2 is opaque – D passes through to N1

  • When CLK = 1

– L2 is transparent, L1 is opaque – N1 passes through to Q

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SLIDE 20

Latch and Flip-flop (two latches)

A latch can be considered as a door CLK = 0, door is shut CLK = 1, door is unlocked A flip-flop is a two door entrance CLK = 1 CLK = 0 CLK = 1

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CLK D Q Q CLK D Q Q Q Q D N1 CLK L1 L2

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SLIDE 21

D Flip-Flop vs. D Latch

CLK D Q Q

D Q Q

CLK D Q (latch) Q (flop) 21

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SLIDE 22

D Flip-Flop vs. D Latch

CLK D Q Q

D Q Q

CLK D Q (latch) Q (flop) 22

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SLIDE 23

D Flip-Flop (Delay)

D CLK Q Q’

Id D Q(t) Q(t+1) 0 0 0 0 1 0 1 0 2 1 0 1 3 1 1 1

Characteristic Expression Q(t+1) = D(t)

0 0 1 1 0 1 PS D 0 1 State table NS= Q(t+1)

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What does the equation mean?

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SLIDE 24

iClicker

24

How long does a D-flip flop store a bit before its

  • utput can potentially change?
  • A. Half a clock cycle
  • B. One clock cycle
  • C. Two clock cycles
  • D. There is no minimum time
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SLIDE 25

Rising vs. Falling Edge D Flip-Flop

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D Q ’ Q Q ’ D Q Symbol for rising-edge triggered D flip-flop Symbol for falling-edge triggered D flip-flop

Clk

rising edges

Clk

falling edges Internal design: Just invert servant clock rather than master The triangle means clock input, edge triggered

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SLIDE 26

Internal Circuit D Q CLK EN D Q 1 D Q EN Symbol

  • Inputs: CLK, D, EN

– The enable input (EN) controls when new data (D) is stored

  • Function

– EN = 1: D passes through to Q on the clock edge – EN = 0: the flip-flop retains its previous state

Enabled D-FFs

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SLIDE 27

27

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SLIDE 28

Bit Storage Overview

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D flip-flop D latch master D latch servant Dm Qm C m Ds D Clk Qs’ Cs Qs Q ’ Q S R D Q C D latch

Only loads D value present at rising clock edge, so values can’t propagate to other flip- flops during same clock cycle. Tradeoff: uses more gates internally than D latch, and requires more external gates than SR – but gate count is less of an issue today. SR can’t be 11 if D is stable before and while C=1, and will be 11 for only a brief glitch even if D changes while C=1. Problem: C=1 too long propagates new values through too many latches: too short may not enable a store.

S1 R1 S Q C R Level-sensitive SR latch

S and R only have effect when C=1. We can design outside circuit so SR=11 never happens when C=1. Problem: avoiding SR=11 can be a burden.

R (reset) S (set) Q SR latch

S=1 sets Q to 1, R=1 resets Q to 0. Problem: SR=11 yield undefined Q.

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SLIDE 29

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SLIDE 30

Shift register

  • Holds & shifts samples of input

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D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK

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SLIDE 31

Pattern Recognizer

  • Combinational function of input samples

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D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK OUT

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SLIDE 32

Counters

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D Q D Q D Q D Q IN OUT1 OUT2 OUT3 OUT4 CLK

  • Sequences through a fixed set of patterns