Logical and Physical Restructuring of Fan-in Trees Hua Xiang - - PowerPoint PPT Presentation

SLIDE 1

Logical and Physical Restructuring of Fan-in Trees

Hua Xiang Haoxing Ren Louise Trevillyan Lakshmi Reddy+ Ruchir Puri Minsik Cho

I BM T.J. Watson Research Center

+ I BM EDA Lab. STG

SLIDE 2

Introduction

 As feature sizes shrink and design complexity

increases, the use of integrated logic synthesis and physical design is expanding.

 Tree restructure for SFFT (Symmetric-Function

Fan-in Tree)

 Trees are created during logic synthesis without

placement information

 Tree placement may be far from optimal since tree

structure is fixed during physical design

 Tree restructure can produce a more placeable and

wire-efficient design.

SLIDE 3

Symmetric-Function Fan-in Tree (SFFT)



A symmetric-function fan-in tree is a fanout-free logic cone



Compute a symmetric function



All of the leaf nets in its support set are commutative



The tree can be implemented with various structures of a uniform set of gates (i.e., AND, OR, XOR)



SFFT trees are frequently found in designs, especially when the design

• riginated as two-level logic



Rebuild SFFT trees based on the placement information to reduce wire length

AND AND AND AND AND

Ga Gb Gc Gn Gd

b a c e f g h l

AND AND AND AND AND

Ga Gb Gc Gn Gd

b a c e f g h l

AND AND AND AND

Ga Gb Gc Gn

b a c e f g h l

F=a·b·c·e·f·g·h·l

SLIDE 4

Tree Restructure

 Algorithm outline

SFFT_Restructure (TreeRoot, Threshold)

1. Identify SFFT tree with root TreeRoot 2. Get the locations of all leaf pins and root pin 3. If # leaf pins < Threshold 4. Apply Dynamic programming based algorithm 5. else 6. Apply Steiner-Tree based restructure algorithm 7. Output the new SFFT tree

SLIDE 5

AND SFFTs

 Possible gates in AND SFFTs

 Any gates whose logic can be expressed by

AND/NOT operations

F = a·b·c·d·e·f

Gate Type Function AND NAND OR NOR NOT BUF

F = a F = a·b F = a·b F = a F = a·b F = a·b

b f

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6

e

G4

AND

G5

d c

SLIDE 6

 Build look-up table to convert

gates to AND/NOT gates

 Build the initial stack based on

the tree root

 Traverse from top to bottom to

identify tree nodes

 Traverse stops

 Multiple-pin net  Infeasible gates  Invalid logic

Stack-based Tree Identification

b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and

Latch

G9

c j . . k . . . . . b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and

Latch

G9

c j . . k . . . . .

and not

b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and not

Latch

G9

c j . . k . . . . . b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and not

Latch

G9

c j . . k . . . . .

and not not and

b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and not

Latch

G9

c j . . k . . . . .

and and

b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and not and

Latch

G9

c j . . k . . . . . b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6 G7

OR

e g h f

G4

. .

AND

G5

i

NAND

G8

and and and not and and and and not and and not and

Latch

G9

c j . . k . . . . . b d

NAND

G1

a

INV NOR

G2

NAND

G3

AND

G6

g h f

G4

AND

G5

i c e j k

SLIDE 7

Tree Restructure

 Rebuild SFFT trees for shorter wire length

 Keep the leaf input nets and root output net unchanged  Remove all internal gates/nets  Use AND/NOT gates to rebuild the tree

 Restructure algorithms

 Dynamic programming based restructure

 Optimal solution for a given tree  Long runtime

 Steiner-Tree based restructure

 The new tree follows the shape of a Steiner Tree for shorter

wire length

 Build sub-trees with DP based tree restructure  Balance quality and runtime

SLIDE 8

DP based Tree Restructure

SFFT_DP (TreeRoot)

• 1. Build connectivity graph
• 2. Let each leaf/Steiner node be a tree,

and push them to Queue

• 3. While (!Queue.empty) {
• 4. subtree = Queue.pop_front
• 5. for parent node P of subtree.TreeRoot
• 6. merge trees related to P with subtree
• 7. prune redundant trees
• 8. push the new trees in Queue
• 9. }
• 10. Return a tree at TreeRoot with

max leaf set and min wire length

(1) (2) (3) (4) (5) (6)

T1

R

T2 T3 T4 S1 S2 T1

R

T2 T3 T4 S1 S2 T1

R

{T1} {R} T2 {T2} T3 {T3} T4 {T4} S1 {S1} S2 {S2} T1

R

{T1} S1 S2

T1}} {{S2},{S2 {{S1},{S1 T1}} {{R},{R T1}}

S1

{S1 T1 T2}} {{S1},{S1 T1}, {S1 T2},

T1

R

T2 T3 T4 S2 T1

R

T2 T3 T4 S1 S2

SLIDE 9

Steiner Tree based Restructure

root T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 root T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 T2 S2 S3 S4 S5 S6 S7 root (0, 11) (1, 10) (2, 1) (1, 1) (2, 9) (3, 1) (3, 8) (4, 3) (5, 1) (5, 1) (5, 1) (5, 2) (4, 5) (5, 2) (6, 1) (6, 1) (5, 1) (6, 1) (6, 1)

(level, children)

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 S1 S2 S3 S4 S5 S6 S7 root (0, 11) (1, 10) (2, 1) (1, 1) (2, 9) (3, 1) (3, 8) (4, 3) (5, 1) (5, 1) (5, 1) (5, 2) (4, 5) (5, 2) (6, 1) (6, 1) (5, 1) (6, 1) (6, 1)

(level, children)

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 S1 S2 S3 S4 S5 S6 S7 root(0, 7) (1, 6) (2, 1) (1, 1) (2, 5) (3, 1) (3, 4) (4, 3) (5, 1) (5, 1) (5, 1) (4, 1)

(level, children)

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 S1 S2 S4 S5 S6 S7 root(0, 7) (1, 6) (2, 1) (1, 1) (2, 5) (3, 1) (3, 4) (4, 3) (5, 1) (5, 1) (5, 1) (4, 1)

(level, children)

T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 S1 S2 S4 S5 S6 S7 root(0, 4) (1, 3) (2, 1) (1, 1) (2, 2) (3, 1) (3, 1)

(level, children)

T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 T2 S2 S4 S5 S6 S7 root (3, 1)

(level, children)

T1 T3 T4 T5 T6 T7 T8 T9 T10 T11 T2 S2 S4 S5

(1) (2) (3) (4) (5) (6) (7) (8)

SLIDE 10

Experimental Results

 Algorithms were implemented in C, and have been

integrated into a physical-synthesis system

 Tested on linux workstations (2.6GHz)  Test cases were derived from industrial designs

SLIDE 11

Experimental Results (cont)

STWL: Total wire length of SFFT trees TWL: Total wire length AEC: Average edge congestions ANC: Average net congestions AEC20: AEC20: Average Edge Congestions of top 20% congested edges ANC20: AEC20: Average Net Congestions of top 20% congested nets Net90:

Number of nets whose congestion ≥ 90%

Net100:

Number of nets whose congestion ≥ 100%

Restructuring Results with Re-placement

SLIDE 12

Experimental Results (cont)

STWL: Total wire length of SFFT trees TWL: Total wire length AEC: Average edge congestions ANC: Average net congestions AEC20: AEC20: Average Edge Congestions of top 20% congested edges ANC20: AEC20: Average Net Congestions of top 20% congested nets Net90:

Number of nets whose congestion ≥ 90%

Net100:

Number of nets whose congestion ≥ 100%

Restructuring Results with Legalization

SLIDE 13

Experimental Results (cont)

(a) Original Tree

Wire Length: 5627

(b) Steiner Tree

Wire length: 1594

(c) Restructured Tree

Wire Length: 2719

(d) Legalized Tree

Wire Length: 2523

SLIDE 14

Conclusion

 SFFT tree is a fanout-free cone of logic

that computes a symmetric function, so that all of the leaf nets in its support set are commutative.

 Propose efficient algorithms to identify

SFFT trees and restructure them.

 SFFT tree restructure helps to get better

tree shapes, reduce wire length and congestion on some designs.