Matrix-Multiply FSMD Start Din WEn WEn Cnt=0 WAddr WAddr - - PowerPoint PPT Presentation

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Matrix-Multiply FSMD Start Din WEn WEn Cnt=0 WAddr WAddr - - PowerPoint PPT Presentation

Matrix-Multiply FSMD Start Din WEn WEn Cnt=0 WAddr WAddr Start=0 S1 Sum=0 RegFile RegFile (RFA) (RFB) Rst Start=1 Counter Inc REn REn (Cnt) RAddr RAddr Cnt=63 i j k RFB(j,k)=Din Cnt=0 S3 S2 Cnt = Cnt +1 Rst Rst Reg


slide-1
SLIDE 1

Matrix-Multiply FSMD

S1 S3 S2 S5 S4 S6 S8 S7 S9 Start=1 Cnt<63 Cnt=63 k=7 k<7 Cnt<511 S10 RFB(j,k)=Din A = RFA(i,k) P=A*B Sum=P+Sum RFC(i,j)=Sum Dout = RFC(j,k) B = RFB(k,j) Cnt=0 Sum=0 Cnt=0 Cnt = Cnt +1 Cnt=0 Cnt=511 Cnt<63 Cnt=63 Sum=0 Cnt = Cnt +1 Cnt = Cnt +1 Done=1 Start=0 RegFile (RFB) RegFile (RFA) RegFile (RFC)

Adder

Reg (Sum)

Multiplier

Counter (Cnt) Din Dout

WAddr RAddr

Reg (A) Reg (B) Reg (P)

Rst Inc WEn REn Ld Rst Ld Rst Ld Rst Ld Rst WEn WAddr REn RAddr

Controller Start Done Comparator

j k Eq511 Eq63 i REn RAddr WAddr WEn

slide-2
SLIDE 2

Matrix Storage

j = 0 1 2 3 4 5 6 7 i = 0 i = 2 i = 3 i = 4 i = 5 i = 6 i = 7 i = 1 00 02 01 76 77 A (i,k) x B (k,j) Counter: j i k

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SLIDE 3

Matrix-Multiply Controller

RegFile (RFB) RegFile (RFA) RegFile (RFC)

Adder

Reg (Sum)

Multiplier

Counter (Cnt) Din Dout

WAddr RAddr

Reg (A) Reg (B) Reg (P)

Rst Inc WEn REn Ld Rst Ld Rst Ld Rst Ld Rst WEn WAddr REn RAddr

Controller Start Done Comparator

j k Eq511 Eq63 i REn RAddr WAddr WEn

S1 S3 S2 S5 S4 S6 S8 S7 S9 Start=1 Cnt<63 Cnt=63 k=7 k<7 Cnt<511 S10 RFB(j,k)=Din, Cnt = Cnt +1 A = RFA(i,k) (RFA_REn=1, RFA_RAddr=(8i+k), A_Ld=1) P=A*B (P_Ld-1, XXX_WEn=0, Sum_Ld=0, Cnt_Inc=0,... ) Sum=P+Sum (Sum_Ld=1, XXX_WEn=0, Cnt_Inc=0, …) RFC(i,j)=Sum, Sum = 0 (RFC_WEn=1, RFC_RAddr=(8i+j), Sum_Rst=1, ...) Dout = RFC(j,k) B = RFB(k,j) (RFB_REn=1, RFB_RAddr=(8k+j), B_Ld=1) Cnt=0 Cnt=0 Sum=0 Cnt=0 Cnt=511 Cnt<63 Cnt=63 Cnt = Cnt +1 Cnt = Cnt +1 (Cnt_Inc=1, …) Done=1 (XXX_WEn=0, Sum_Ld=0, Cnt_Inc=0, . . .) Start=0

slide-4
SLIDE 4

S5 S4 S6 S8 S7 Cnt<63 k=7 k<7 Cnt<511 A = RFA(i,k) (RFA_REn=1, RFA_RAddr=(8i+k), A_Ld=1) P=A*B (P_Ld-1, XXX_WEn=0, Sum_Ld=0, Cnt_Inc=0,... ) Sum=P+Sum (Sum_Ld=1, XXX_WEn=0, Cnt_Inc=0, …) RFC(i,j)=Sum, Sum = 0 (RFC_WEn=1, RFC_RAddr=(8i+j), Sum_Rst=1, ...) B = RFB(k,j) (RFB_REn=1, RFB_RAddr=(8k+j), B_Ld=1) Cnt=0 Cnt=511 Cnt = Cnt +1 (Cnt_Inc=1, …) ( XXX_WEn=0, Sum_Ld=0, Cnt_Inc=0,... )

RegFile (RFB) RegFile (RFA)

Adder

Reg (Sum)

Multiplier

Counter (Cnt)

WAddr RAddr

Reg (A) Reg (B) Reg (P)

Rst Inc WEn REn Ld Rst Ld Rst Ld Rst Ld Rst WEn WAddr REn RAddr

Comparator

j k Eq511 Eq63 i

slide-5
SLIDE 5

Matrix-Multiply Structure

ENTITY MatrixMult IS PORT ( Clk : in std_logic; Start : in std_logic; Din : in INTEGER; Done : out std_logic; Dout : out INTEGER ); END MatMul; ARCHITECTURE MatrixMult_struct OF MatrixMult IS COMPONENT Multiplier IS … COMPONENT Adder IS … COMPONENT Counter IS … COMPONENT Comparator IS … COMPONENT Reg is … COMPONENT RegFile IS … COMPONENT Controller IS … END COMPONENT; SIGNAL Cnt_Inc, Cnt_Rst, Sum_Ld, Sum_Rst:std_logic; SIGNAL A_Ld, A_Rst, B_Ld, B_Rst:std_logic; SIGNAL mult_out: INTEGER; SIGNAL adder_out, : INTEGER; SIGNAL i_s, j_s, k_s: std_logic_vector(2 downto 0); … BEGIN Sum: Reg PORT MAP ( ……… ); A: Reg PORT MAP (…………); B: Reg PORT MAP (…………); P: Reg PORT MAP (…………); Controller_1: Controller PORT MAP (…………); RFA: RegFile PORT MAP (…………); RFB: RegFile PORT MAP (…………); RFC: RegFile PORT MAP (…………); Counter_1: Counter PORT MAP (…………); Comparator_1: Comparator PORT MAP (………); Mult_1: Multiplier PORT MAP (……………); Adder_1: Adder PORT MAP (……………); END MatrixMult_struct;

RegFile (RFB) RegFile (RFA) RegFile (RFC)

Adder

Reg (Sum)

Multiplier

Counter (Cnt) Din Dout

WAddr RAddr

Reg (A) Reg (B) Reg (P)

Rst Inc WEn REn Ld Rst Ld Rst Ld Rst Ld Rst WEn WAddr REn RAddr

Controller Start Done Comparator

j k Eq511 Eq63 i