Memory Errors Bits in memory can be flipped Hard error The chip is - - PowerPoint PPT Presentation
Verilog Memory Errors Bits in memory can be flipped Hard error The chip is broken E.g., manufacturing defect, wear (in Flash) Soft error Stored data corrupted, but cell still works Caused by atmospheric neutrons, alpha
Verilog
Digital Design — Chapter 5 — Memories 1
Bits in memory can be flipped Hard error
The chip is broken E.g., manufacturing defect, wear (in Flash)
Soft error
Stored data corrupted, but cell still works Caused by atmospheric neutrons, alpha particles,
Soft-error rate
frequency of occurrence
Verilog
Digital Design — Chapter 5 — Memories 2
Add a parity bit to each location On write access
compute data parity and store with data
On read access
check parity, take exception on error
If we could tell which bit flipped
correct by flipping it back, then write back
Can’t do this with parity
Verilog
Digital Design — Chapter 5 — Memories 3
Allow identification of the flipped bit Hamming Codes
E.g., for single-bit-error correction of N-bit word,
Example: 8-bit word, d1... d8
12-bit ECC code, e1...e12 e1, e2, e4, e8 are check bits, the rest data
d1 d2 d3 d4 d5 d6 d7 d8 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12
Verilog
Digital Design — Chapter 5 — Memories 4
e1 1 e2 1 e4 1 e8 1 e3 1 1 e5 1 1 e6 1 1 e7 1 1 1 e9 1 1 e10 1 1 e11 1 1 1 e12 1 1
Every data bit covered by two
On write: Compute check bits
d1 d2 d3 d4 d5 d6 d7 d8 e1 e2 e3 e4 e5 e6 e7 e8 e9 e10 e11 e12
Verilog
Digital Design — Chapter 5 — Memories 5
e1 1 e2 1 e4 1 e8 1 e3 1 1 e5 1 1 e6 1 1 e7 1 1 1 e9 1 1 e10 1 1 e11 1 1 1 e12 1 1
On read: Recompute check bits
result called the syndrome
0000 => no error If data bit flipped
covering bits of syndrome are 1 = binary code of flipped ECC bit
If stored check bit flipped
that bit of syndrome is 1
On error, unflip bit and rewrite
Verilog
Digital Design — Chapter 5 — Memories 6
What if two bits flip
syndrome identifies wrong bit, or is invalid
One extra check bit allows
single-error correction, double-error detection
N Single-bit correction Double-bit detection Check bits Overhead Check bits Overhead 8 4 50% 5 63% 16 5 31% 6 38% 32 6 19% 7 22% 64 7 11% 8 13% 128 8 6.3% 9 7.0% 256 9 3.5% 10 3.9%
Verilog
Digital Design — Chapter 5 — Memories 7
Memory: addressable storage locations Read and Write operations Asynchronous RAM Synchronous RAM (SSRAM) Dynamic RAM (DRAM) Read-Only Memory (ROM) and Flash Multiport RAM and FIFOs Error Detection and Correction
Hamming Codes