Multicore Multicore curiculum 1 Motivation Moores Law: the number - PowerPoint PPT Presentation
Multicore Multicore curiculum 1 Motivation Moores Law: the number of transistors double every 18 months Fonte: Intel Multicore curiculum 2 Memory capacity also increases Multicore curiculum 3 The Memory Wall 100,000 10,000 1,000
Multicore Multicore curiculum 1
Motivation Moore’s Law: the number of transistors double every 18 months Fonte: Intel Multicore curiculum 2
Memory capacity also increases Multicore curiculum 3
The Memory Wall 100,000 10,000 1,000 Performance CPU 100 10 Memory 1 Year Multicore curiculum 4
How to go parallel? • VLIW Processors • Superescalar Processors – Hyperthread • Multi-core Multicore curiculum 5
Very Long Instruction Word Instruction (8 operations) Time Processor (8 Functional Units) Multicore curiculum 6
VLIW • Advantages – Easy to implement in hardware • Several similar tiles • Do not require a huge control logic • Disadvantages – Difficult to generate good code Multicore curiculum 7
Superscalar Processor Instructions ? Time Processor (8 Functional Units) Multicore curiculum 8
Superscalar Processor • Advantage – Transparent to the software – The processor is able to use dynamic information to find the parallelism – Speculative code execution • Disadvantage – Can not always find instruction for each functional unit – Detecting parallelism in hardware requires a lot of area Multicore curiculum 9
Hyperthreading Technology P1 (4 FU) P2 (4 FU) P1 + P2 + = Time Multicore curiculum 10
Hyperthreading Technology • Requirements – 2 Different • Program counter • Register banks • Status registers – The same • Functional units • Caches Multicore curiculum 11
Hyperthreading Technology • Advantage – Uses the available functional units to execute a second thread – Capable of executing code during a stall of the other thread (cache miss, etc) • Disadvantage – Threads usually need the same functional unit – 2 threads at the same time, but only 30% of typical speedup Multicore curiculum 12
Chip Multiprocessing (CMP) 2 Cores 4 Cores Core 1 Core 2 Core 1 Core 2 Core 3 Core 4 L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L1 Cache L2 Cache L2 Cache A cache L2 também pode ser dividida! Multicore curiculum 13
Pentium D Processor Diagram Multicore curiculum 14
Intel Dual Core Pentium Multicore curiculum 15
Intel Roadmap Multicore curiculum 16
AMD Dual Core Multicore curiculum 17
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