MUSTARD: A CAD tool for Predicting the Impact of Random Telegraph - - PowerPoint PPT Presentation

mustard a cad tool for predicting the impact of random
SMART_READER_LITE
LIVE PREVIEW

MUSTARD: A CAD tool for Predicting the Impact of Random Telegraph - - PowerPoint PPT Presentation

MUSTARD: A CAD tool for Predicting the Impact of Random Telegraph Noise on SRAMs and DRAMs Karthik Aadithya (aadithya@berkeley.edu) Joint work with Alper Demir, Koc University, Istanbul, Turkey Sriramkumar Venugopalan, UC Berkeley Jaijeet


slide-1
SLIDE 1

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 1/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD: A CAD tool for Predicting the Impact of Random Telegraph Noise on SRAMs and DRAMs Karthik Aadithya

(aadithya@berkeley.edu)

Joint work with

Alper Demir, Koc University, Istanbul, Turkey Sriramkumar Venugopalan, UC Berkeley Jaijeet Roychowdhury, UC Berkeley

slide-2
SLIDE 2

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 2/20 2014/03/17, Designing with Uncertainty Workshop, York

Overview of this talk

  • Why worry about RTN? (SRAMs, DRAMs)
  • RTN basics
  • Our contributions: RTN+circuit co-simulation
  • discrete Monte-Carlo ↔ nonlinear ckt. simulation
slide-3
SLIDE 3

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 3/20 2014/03/17, Designing with Uncertainty Workshop, York

Importance of SRAMs and DRAMs

Core i7 die

Laptop, desktop, tablet memories Billions of DRAM cells Cache memory (L1, L2, L3, etc.) Millions of SRAM cells

slide-4
SLIDE 4

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 4/20 2014/03/17, Designing with Uncertainty Workshop, York

6T SRAM cell: Write Operation

  • Writing a 1 to the SRAM cell
  • Switch BL to high, BL_bar to low
  • Briefly enable WL
  • By the end of the clock cycle
  • Q should settle to 1
  • Q_bar should settle to 0
  • Cross-coupled inverter pair will

maintain this (stable) state

  • Key idea: Back-to-back inverters
slide-5
SLIDE 5

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 5/20 2014/03/17, Designing with Uncertainty Workshop, York

How RTN can impact SRAM write

RTN can induce dynamic SRAM write failure! (read failures also reported)

slide-6
SLIDE 6

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 6/20 2014/03/17, Designing with Uncertainty Workshop, York

RTN in SRAMs: Experimental Evidence

Measured data

  • Confirms temporal SRAM failures due to RTN
  • Quantifies RTN in terms at circuit level
  • Fig. Credit: Seng O. Toh, PhD thesis, UCB

Write to SRAM Read from SRAM. Record errors. Select Vdd For each , record min, max fail bit count

Vdd

Vdd

slide-7
SLIDE 7

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 7/20 2014/03/17, Designing with Uncertainty Workshop, York

Noise: An SRAM designer's viewpoint

Figure credits: Y. Tsukamoto, Renesas Electronics Corp.

RTN impact is steadily increasing! At 22nm, RTN can drive design margins negative!

RTN-induced SRAM failures experimentally reported

Seng et. al. (IEDM 2009), Yas et. al. (IRPS 2010)

slide-8
SLIDE 8

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 8/20 2014/03/17, Designing with Uncertainty Workshop, York

What causes RTN?

Capture Release Random Processes

Filled traps modify number, mobility

  • f electrons in inversion layer

Change in drain current Measured as RTN

slide-9
SLIDE 9

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 9/20 2014/03/17, Designing with Uncertainty Workshop, York

RTN is Non-Stationary

Bias-dependence leads to non-stationary RTN Capture Release

V_gs Hz

slide-10
SLIDE 10

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 10/20 2014/03/17, Designing with Uncertainty Workshop, York

RTN: Bridging the Gap ?

CAD tool incorporating device level RTN models for circuit level non-stationary RTN characterisation Device level RTN models Circuit level RTN measurements

MUSTARD

slide-11
SLIDE 11

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 11/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD's RTN Model

Core idea: Simulate the bi-directionally coupled MC-DAE system using an intelligent Monte-Carlo scheme

Markov chain (RTN)

Coupled

Markov state affects DAE's q(.), f(.)

Differential Algebraic Equations (Rest of the circuit)

  • ngoing DAE solution

affects Markov propensities

Discrete Stochastic Continuous Deterministic

slide-12
SLIDE 12

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 12/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD: Non-stationary Trap Simulation with Bi-Directional Coupling

Keep → update rate … and so on Keep → update rate Discard → don't update rate

slide-13
SLIDE 13

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 13/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD: Simulation Methodology

Generate candidate RTN event Start Simulate circuit until event Probabilistically decide: keep (or) discard event? Update circuit equations Keep! Discard Discard Keep

Exact, non-stationary statistics preserved!

slide-14
SLIDE 14

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 14/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD: Individual SRAM cell

No RTN No V_th variability No RTN Yes V_th variability Yes RTN Yes V_th variability

slide-15
SLIDE 15

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 15/20 2014/03/17, Designing with Uncertainty Workshop, York

RTN+Variability: MUSTARD on 6T SRAM across (VDD,Vth) landscape

Without RTN With RTN

slide-16
SLIDE 16

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 16/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD-generated BER vs VDD plots

  • asdf
slide-17
SLIDE 17

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 17/20 2014/03/17, Designing with Uncertainty Workshop, York

MUSTARD: RTN Effects on DRAMs

  • asdf
slide-18
SLIDE 18

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 18/20 2014/03/17, Designing with Uncertainty Workshop, York

Summary and Conclusions

  • RTN is a concern for SRAM scaling
  • Bottom-up prediction of bit errors challenging
  • discrete random events + non-stationarity + “feedback”
  • MUSTARD offers a simulation-based solution
  • strong mathematical guarantee on accuracy: applies to
  • any trap configuration
  • any circuit (SRAM, DRAM, etc.)
  • any device model, any model for RTN, etc.
slide-19
SLIDE 19

Karthik Aadithya, UC Berkeley (aadithya@berkeley.edu) Slide 19/20 2014/03/17, Designing with Uncertainty Workshop, York

Publications

(1) Aadithya V Karthik, Alper Demir, Sriramkumar Venugopalan and Jaijeet

  • Roychowdhury. SAMURAI: An accurate method for modelling and simulating

non-stationary Random Telegraph Noise in SRAMs. In Proceedings of the Design, Automation and Test Conference in Europe, 2011. (2) Aadithya V Karthik, Sriramkumar Venugopalan, Alper Demir and Jaijeet

  • Roychowdhury. MUSTARD: A coupled, stochastic-deterministic,

discrete-continuous technique for predicting the impact of Random Telegraph Noise on SRAMs and DRAMs. In Proceedings of the Design Automation Conference 2011. (3) Aadithya V Karthik, Alper Demir, Sriramkumar Venugopalan, and Jaijeet

  • Roychowdhury. Accurate Prediction of Random Telegraph Noise Effects in

SRAMs and DRAMs. In the 2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 32, Issue 1.