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On- board PCs f or interf acing f ront- end electronics
J COP t eam meet ing
April 10, 2002
Niko Neuf eld CERN/ EP
On- board PCs f or interf acing f ront- end electronics J COP t eam - - PowerPoint PPT Presentation
On- board PCs f or interf acing f ront- end electronics J COP t eam meet ing April 10, 2002 Niko Neuf eld CERN/ EP 1 Controlling Boards The traditional approach Parallel Bus (VME, Fast bus, ) Ethernet Cont rol St at ion Crat e Cont
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Niko Neuf eld CERN/ EP
Niko NEUFELD CERN, EP
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Crat e Cont roller (CPU) Elect ronics Modules Parallel Bus (VME, Fast bus,… )
Ethernet
Niko NEUFELD CERN, EP
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– a f ault y module can block access t o a whole crat e/ chain – t he f ault y module is dif f icult t o isolat e once t he bus is blocked – t he crat e processors / local int erf ace - PC combinat ions are expensive
Niko NEUFELD CERN, EP
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Standard Application Specific
Power Connectors LAN
FPGAs Regs
e.g. 9Ux400mm
LUTs DSPs
Reset
PC
ADCs TDCs etc...
CONTROL INTERFACE access to
components
Only interface to the board
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Niko NEUFELD CERN, EP
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embedded Web servers, digit al TV wit h int egrat ed I nt ernet browsers, swit ching st at ions, elect ronic t elephone books, navigat ion syst ems, passenger ent ert ainment , onboard I nt ernet t erminals, ATMs, vending machines, inf ormat ion t erminals , heart monit ors, blood analyzers, brain act ivit y analyzers, X-ray equipment , comput er-aided t omographs, dat a loggers, machine cont rollers, programmable logic cont rollers (PLCs), mobile dat a input devices, f light calculat ors f or unmanned f light equipment , communicat ions servers, and addit ional ext remely rugged milit ary applicat ions
Niko NEUFELD CERN, EP
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Niko NEUFELD CERN, EP
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Niko NEUFELD CERN, EP
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Standard Application Specific
Power Connectors 100 Mbit Ethernet
FPGAs Regs
E.g. 9Ux400mm
LUTs DSPs
Reset
PC
ADCs TDCs Etc...
CCPC I2C JTAG Parallel Bus PCI Bus GLUE CARD
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Niko NEUFELD CERN, EP
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– more J TAG and I 2C int erf aces (necessit at es addit ional decoder logic on I SA bus) – simpler (cheaper) PLX local bridge (e.g. 9030)
– J TAG (f rom parallel port via Alt era Byt eBlast er) – Parallel local bus via PLX PCI 9080 bridge – Level adapt at ion f or serial port
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PLX PCI 9080 May be covered by f inal glue- board
25 mm
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40 MHz Clk
Shaper
PHOS4 Din Clk in Enc Ain
14 / 4 / Floppy
LAN
6 /
VGA
2 2
MS KB SMART
PCI
Byteblast er JTAG
PLX 9080
12 bit data
Altera
10K50E240 189pin data ad d 512Kx 18
VME Conn
EPM7160-100
Glue Logic JTAG
DATA ADD CONTR Dout C lk Add[18..0] Data[31..16] data ad d 512Kx 18 EEPROM
CY230 8-2
x1 x2
16-bit 80MHz 40MHz LAD[31..0] Control
ADC
CLK 11
I2C
IN 7 select 4
CLK I2C
9042
9 /
COM
J1 J2
Data[15..0]
8 JTAGConn User Conn. J1 J2 J3 RS232
comprising 2 MB of RAM, FPGA, CC-PC, Phos4 I 2C programmable delay
ADC and local bus; it is programmed via J TAG
PC works: the OS boots f rom the internal f lash RAM, runs f rom the network, can access board components
Niko NEUFELD CERN, EP
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