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Optimizing headroom for serial powering, CMS upgrade phase 2 Agathe Nidriche 26/07/2019 Agathe Nidriche Optimization for the Headroom 1 SUMMARY I) Introduction II) Presentation of the modelisation III) 1 FE Chips simulation IV) Study :

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Agathe Nidriche

26/07/2019 Agathe Nidriche – Optimization for the Headroom 1

Optimizing headroom for serial powering, CMS upgrade phase 2

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26/07/2019 Agathe Nidriche – Optimization for the Headroom 2

I) Introduction II) Presentation of the modelisation III) 1 FE Chips simulation IV) Study : Best Configuration, 4 chips V) Study : Best Configuration, 2 chips Conclusion

SUMMARY

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Vin nominal Idig required Iana required

Voff Rdig Rana

Idig Iana Dig headroom (=unused current) Ana headroom (=unused current)

  • We need to give headroom to each Shunt LDO to

prevent the module from powering shortages (increasing of the load (hitrate), chip failure, launching of the clock)…….

  • However giving more headroom means more

power consumption (since all the unused current is shunt to the ground). 𝐽 = 𝐽𝑒𝑗𝑕𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒 ∗ (1 + Headroomdig) + 𝐽𝑏𝑜𝑏𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒 ∗ (1 + Headroomana) V I I) Introduction : Headroom

  • The current sharing (choice of R and Voff) must be

precise to get enough digital and analog headroom.

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The headroom is the difference between the load consumed current and the input current.

Goal : get the best analog and digital headrooms for the lowest global headroom.

I) Introduction : Headroom

  • Global Headroom

𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛𝑕𝑚𝑝𝑐𝑏𝑚 = (𝐽𝑡𝑣𝑞𝑞𝑚𝑧 - 𝐽𝑠𝑓𝑟)/ 𝐽𝑠𝑓𝑟

  • Headroom for the analog SLDO

𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛𝑏𝑜𝑏 = (𝐽𝑡𝑣𝑞𝑞𝑚𝑧𝑏𝑜𝑏−𝐽𝑠𝑓𝑟𝑏𝑜𝑏)/ 𝐽𝑠𝑓𝑟𝑏𝑜𝑏

  • Headroom for the digital SLDO

𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛𝑒𝑗𝑕 = (𝐽𝑡𝑣𝑞𝑞𝑚𝑧𝑒𝑗𝑕−𝐽𝑠𝑓𝑟𝑒𝑗𝑕)/ 𝐽𝑠𝑓𝑟𝑒𝑗𝑕

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𝐽𝑡𝑣𝑞𝑞𝑚𝑧 + ෍ 𝑊

𝑗

𝑆𝑗 ෍ 1 𝑆𝑗 = Vmodule 𝐽𝑇𝑀𝐸𝑃 = 𝑊 − 𝑊

𝑝𝑔𝑔 𝑇𝑀𝐸𝑃

𝑆𝑇𝑀𝐸𝑃 𝐼𝑓𝑏𝑒𝑠𝑝𝑝𝑛𝑇𝑀𝐸𝑃 =

𝐽𝑇𝑀𝐸𝑃 𝐽𝑠𝑓𝑟𝑣𝑗𝑠𝑓𝑒-1

4-SLDOs module = 2-Chips module Formula that caracterize the module

Analog SLDO Analog SLDO Digital SLDO Digital SLDO

Chip1 Chip2 II) Presentation of the modelisation : Circuit

𝐽𝑡𝑣𝑞𝑞𝑚𝑧 = (෍ 𝐽𝑇𝑀𝐸𝑃) ∗ (1 + Headroomglobal)

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One FE Chip = 1 analog and 1 digital part.

Analog part requires 1.0 A Digital part requires 0.5 A.

Chip level : We consider that one FE Chip is composed of 2 SLDOs with the same

  • ffsets and different slopes.

Module level : We consider that each chip on the module is composed of the same SLDOs

How can we chose the resistances and offsets of the Shunt LDOs such that each SLDO gets enough headroom ?

One FE Chip

Analog SLDO Digital SLDO

II) Presentation of the modelisation : FE Chip

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For all simulations, we decide that the module works if it fits the considered conditions :

  • Vmodule>1,45V (a)
  • Vmodule<2V if one chip fails (b)
  • The headroom for the analog SLDO is over 10% (Headroom_ana>10%)
  • The headroom for the digital SLDO is over 10% (Headroom_dig>10%)

This is one of the most basic scenarios concerning headroom issues, it underevaluates reality.

>1,45V <2V

Case (a) Case (b)

II) Presentation of the modelisation : Circuit working conditions

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Allowed region

Vmodule<1,45V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

III) Simulation : 1 Chip, Voff=0.8V, 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1-x)*R
  • R_dig=(1+x)*R

Goal : find the values

  • f resistances R_ana

and R_dig for a fixed Voff=0.8, 1, 1.2 V, that enable the 1-chip- module to work in the previous conditions (ie « Allowed region ») Ex : x=0.3, R=0.7 -> R_dig=0.91 MΩ A_ana=0.49 MΩ

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Allowed region

Vmodule<1,45V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

III) Simulation : 1 Chip, Voff=1V , 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1-x)*R
  • R_dig=(1+x)*R
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Allowed region

Vmodule<1,45V Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

III) Simulation : 1 Chip, Voff=1.2V , 20% headroom

Headroom_ana<10% And Vfailure>2V

Vfailure>2V

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1-x)*R
  • R_dig=(1+x)*R
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IV) Study : Best Configuration, 4 chips : Allowed regions V_offset, V Headroo m 1,2 1 0,8 25% 20% 15%

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IV) Study : Best Configuration, 4 chips : Power Limitation V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 %

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IV) Study : Best Configuration, 4 chips : Resistance mismatch limitation. V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 %

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IV) Study : Best Configuration, 4 chips : Offset mismatch limitation. V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 %

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IV) Study : Best Configuration, 4 chips : 2 chips failure limitation. V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 % Case of 2 chips failure : No resistances can enable the module to work for 0.8 offset voltage (Works better for 1.2V than 1V). V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 %

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IV) Study : Best Configuration, 4 chips : Conclusion . Best offset value to work in every headroom conditions V_offset, V Headr

  • om

1,2 1 0,8 25% 20% 15%

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IV) Study : Best Configuration, 4 chips : Conclusion.

Optimal resistance values ([R_dig,R_ana]) for nominal work for 15% and 20% and 25% headroom :

[0.966, 0.500] (MΩ)

Overlap

1 V offset 1 V offset

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IV) Study : Best Configuration, 4 chips : Conclusion.

Optimal resistance values ([R_dig,R_ana]) for nominal work for 15% and 20% and 25% headroom :

[0.639, 0.350] (MΩ) 1.2 V offset

Overlap

1.2 V offset

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V) Study : Best Configuration, 2 chips. Voffset Headro

  • m

1 V 1.2 V 25 % 20 % 15 %

Overlap Overlap

1V

  • ffset

1.2V

  • ffset
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Voffset 1V 1.2V Power consumption,W Maximum tolerated percentage of mismatch, Voff. Maximum tolerated percentage of mismatch, resistance.

26/07/2019 Agathe Nidriche – Optimization for the Headroom 20

V) Study : Best Configuration, 2 chips.

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V) Study : Best Configuration, 2 chips: Conclusion.

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Overall conclusion Optimal Voffset Range of R_dig Range of R_ana Headroom Tolerated

  • ffset

mismatch Tolerated resistance mismatch Quadr Chip module 1 V [0.4,0.8] [0.7,1.2] 15%-25% 4% 7% Those two resistances are coupled. Double Chip module 1.2 V [0.2,0.4] [0.45,0.65] 15%-25% 3.5% 8% Those two resistances are coupled.

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Backup Slides

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Chart : Different efficiency regions on the graph Region Headroom_dig<headro

  • m_threshold_dig

V_fail[j,i]>V_fail_max V[j,i]<Vmin Headroom_ana<headro

  • m_threshold_ana

1 X 2 X 3 X X 4 X 5 X X 6 X X 7 X X X 8 X 9 X X 10 X X 11 X X X 12 X X 13 X X X 14 X X X 15 X X X X

Caracterization of the module efficiency

Pourcentage of discrepancy between slopes, x 26/07/2019 Agathe Nidriche – Optimization for the Headroom 24

Backup Slides : Different states of the module

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Vmodule<1,45V Vfailure>2V

Headroom_ana<10%, Vfailure>2V Vmod<1.45 Headroom_ana<10% And Vmod<1.45 V Headroom_ana<10% And Vfailure>2V Headroom_dig < 10% And Vmod<1,45 V Headroom_dig< 10% And Vfailure>2V And Vmod<1.45 V

Two chips : 0.8 V offset isn’t enough to find resistances that enable a good sharing of the current NO ALLOWED REGION

Backup Slides : Simulation : 2 Chips, Voff=0.8V , 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

20% headroom

Vfailure>2V and Vmodule<1,45V

Goal : find the values

  • f resistances R_ana

and R_dig for a fixed Voff=0.8, 1, 1.2 V, that enable the 2-chips- module to work in the previous conditions (ie « Allowed region »)

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Allowed region

Vmodule<1,45V Vfailure>2V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ana<10% And Vfailure>2V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V Headroom_dig< 10% And Vfailure>2V

Backup Slides : Simulation : 2 Chips, Voff=1V , 20% headroom 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

2 Chips

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Allowed region

Vmodule<1,45V Vfailure>2V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ana<10% And Vfailure>2V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V Headroom_dig< 10% And Vfailure>2V

Backup Slides : Simulation : 2 Chips, Voff=1.2V , 20% headroom 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

2 Chips

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Allowed region

Vmodule<1,45V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

Goal : find the values

  • f resistances R_ana

and R_dig for a fixed Voff=0.8, 1, 1.2 V, that enable the 4-chips- module to work in the previous conditions (ie « Allowed region ») Backup Slides : Simulation : 4 Chips, Voff=0.8V , 20% headroom 20% headroom 4 Chips

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Allowed region

Vmodule<1,45V Vfailure>2V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ana<10% And Vfailure>2V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

Backup Slides : Simulation : 4 Chips, Voff=1V , 20% headroom 20% headroom

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

4 Chips

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Allowed region

Vmodule<1,45V Vfailure>2V

Headroom_ana<10% Headroom_ana<10% And Vmod<1.45 V Headroom_ana<10% And Vfailure>2V Headroom_ dig <10% Headroom_dig < 10% And Vmod<1,45 V

Backup Slides : Simulation : 4 Chips, Voff=1.2V , 20% headroom 20% headroom

Headroom_dig< 10% And Vfailure>2V

  • Abscissa : x
  • Ordonnate : R
  • >
  • R_ana=(1+x)*R
  • R_dig=(1-x)*R

4 Chips

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Global headroom : 15% Global headroom : 10%,

Allowed region Allowed region

Global headroom : 25% No allowed region

Backup Slides : Parametric studies : Global Headroom, 0.8V, 4 chips

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Global headroom : 15% Global headroom : 10%,

Allowed region Allowed region

Global headroom : 25% No allowed region

Backup Slides : Parametric studies : Global Headroom, 1V, 4 chips

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Global headroom : 15% Global headroom : 10%

Allowed region

Allowed region

Global headroom : 25% No allowed region

Backup Slides : Parametric studies : Global Headroom, 1.2V, 4 chips

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Global headroom = 15%,

Headroom ana > 10%, Headroom dig > 10%

Global headroom = 15%,

Headroom ana > 5%, Headroom dig > 5%

Allowed region

Global headroom = 15%,

Headroom ana > 20%, Headroom dig > 20%

Allowed region

No allowed region

Backup Slides : Parametric studies : Analog/Digital Headroom, 4 chips

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Pourcentage of discrepancy between slopes, x

Backup Slides : Parametric studies : Voltage offset (20% global headroom), 4 chips

Allowed region Allowed region

Allowed region Allowed region

Allowed region

Power consumption of the module : 13.81 W Power consumption of the module : 14.03 W Power consumption of the module : 13.24 W

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2 FE Chips simulation : Choice of resistance

  • Good configuration : above 15% global headroom,

10% analog headroom, 10% digital headroom

  • Good configurations; for 10% ana/dig thresholds, 1 V
  • ffset:
  • In case of chip failure, consumed power per chip

jumps by 33% 4 FE Chips simulation : Choice of resistance

  • The range of resistances that can be chosen is widest than

for the 2-chips module.

  • Good configurations, for 10% ana/dig thresholds, 1 V offset

:

  • In case of chip failure, consumed power per chip jumps by

15% Voffset

  • Increasing the offset enables to widen the area of the allowed region, against a higher power consumption

Headroom Exemple of optimal resistances 15% Rdig=0.80, Rana=0.42 20% Rdig=0.77, Rana=0.40 30% Rdig=0.68, Rana=0.38 40% Rdig=0.61, Rana=0.36 Headroom Exemple of optimal resistances 15% Rdig=1.02, Rana=0.53 20% Rdig=0.95, Rana=0.51 30% Rdig=0.85, Rana=0.48 40% Rdig=0.77, Rana=0.45

Backup Slides : Parametric studies : Conclusion

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Backup slides : Digital headroom limitation (20%) : 4 chips V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 % Digital headroom of 20% : In case of a nominal 0.5A current required, enables a 100 mA load on the digital part. V_offset, V He adr

  • m

1,2 1 0,8 25 % 20 % 15 %

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Backup slides : Case of an increasing load : 2 CHIPS MODULE

ANALOG SLDO1 DIGITAL SLDO1 ANALOG SLDO2 DIGITAL SLDO2 Required current (a) 1 A 0.5 A 1 A 0.6 A Required current (b) 1 A 0.5 A 1 A 0.75 A

20% Headroom

ANALOG SLDO1 DIGITAL SLDO1 ANALOG SLDO2 DIGITAL SLDO2 Required current (a) 1 A 0.5 A 1 A 0.6 A Required current (b) 1 A 0.5 A 1 A 0.8 A

25% Headroom 1 analog and 1 digital resistance (a) 1 analog and 2 digital resistances (b) 1 analog and 2 digital resistances (b) 1 analog and 1 digital resistance (a)

ANALOG SLDO1 DIGITAL SLDO1 ANALOG SLDO2 DIGITAL SLDO2 Nominal current 1 A 0.5 A 1 A 0.5 A

Chart besides : nominal current Goal : Find the most extreme overload configuration on one digital SLDO, that still enable the 2-chips-module to operate. Cases : 1 digital resistance, 1 analog resistance for both chips 1 analog resistance for both chips, 2 different digital resistances.

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Different scenarios ANALOG SLDO LOAD DIGITAL SLDO LOAD Nominal load (a) 1 A 0.5 A 500 mA added load on analog part (b) 1.5 A 0.5 A 500 mA added load on digital part (c) 1 A 1 A Which ℎ𝑓𝑏𝑒𝑠𝑝𝑝𝑛𝑕𝑚𝑝𝑐𝑏𝑚 should we chose such that :

  • The supply current is chosen for nominal conditions
  • There is an area that covers the « allowed » area for the three scenarios (a),

(b), (c) We need around 85 % headroom ! 4-chips-module : possible resistances : Rana=0.201, Rdig=0.466 2-chips-module : possible resistances : Rana=0.286, Rdig=0.426 The allowed region is really thin

(a) (b) (c)

The analog SLDO makes the area shrink The digital SLDO makes the area shrink Perfect conditions

85% Headroom Backup slides : Case of an increasing load

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Chose circuit caracteristics and headroom to get correct voltage and headroom for each SLDO Give optimal resistances values for a given offset >15% global headroom Get a margin in case of mismatches of 5% on the circuitry of a chip in the module >30-40% global headroom 2-chips module >20-30% global headroom 4-chips module Get a margin in case of a 500 mA increase of the required current (both ana/dig) >85% global headroom 2-4-chips module Get a margin in case of mismatches (a) up to 5%

  • n each chip (b) 10 % on a

chip >(a) 40% 4 chips, 50% 2 chips >(b) 50% 4 chips 70% 2 chips Global headroom need increases with constraints on the module Basic configuration Light mismatch Strong mismatch Load increasing Conclusion