[PPT] - Ramping New Products Yields Ramping New Products Yields in the Deep PowerPoint Presentation

SLIDE 1

21-Mar-00 • 1 • PDF Solutions, Inc.

Ramping New Products Yields Ramping New Products Yields in the Deep in the Deep Submicron Submicron Age Age

ISQED 2000 March 21st, 2000 PDF Solutions, Inc. John K. Kibarian

SLIDE 2

21-Mar-00 • 2 • PDF Solutions, Inc.

Major Points Major Points

G Increasing design and process complexity becoming

critical factor leading to yield loss

G Systematic yield loss component is significant,

growing, and recoverable

G Fundamental new approach, focused on integration

between design, process and manufacturing, is required to recover yield loss

SLIDE 3

21-Mar-00 • 3 • PDF Solutions, Inc.

Outline Outline

G Product Yield Ramps: the market pressures G The Design-Manufacturing Integration Problem G Solution G Examples G Concluding remarks

SLIDE 4

21-Mar-00 • 4 • PDF Solutions, Inc.

Complexity is Increasing Across the Board Complexity is Increasing Across the Board

IC Complexity: Processing Steps

100 200 300 400 500 600 1997 1999 2002 2005 2008

Processing Steps IC Complexity: Transistors

1 10 100 1,000 1997 1999 2001 2003 2005 2008

Transistors (M)

IP Reuse is IP Reuse is Critical to Get Critical to Get Designs to Market Designs to Market Faster Faster Unless Corrected, Unless Corrected, Increased Processing Increased Processing Complexity Reduces Complexity Reduces Yield up to 5% per Year Yield up to 5% per Year

SLIDE 5

21-Mar-00 • 5 • PDF Solutions, Inc.

The Window is Tightening The Window is Tightening

Years to 1 Million Sales

1 2 3 5 10 15 20 25

Sales Volume 1 Million Units

Playstation II DVD Cellular PC VCR Color TV Cable TV B&W TV PCS 5 10 15 20

1000 2000 3000 4000 5000 12 24 36

Months to Full Production Wafers per Week

Design Rules: 0.13u 0.18u 0.25u 0.35u 0.5u 0.8u Accelerating Ramp Rates

The demand is The demand is accelerating accelerating There is less time There is less time to bring up the to bring up the volume volume

Sources: 1) D. Merriman, “Wireless Comm. Report”, BIS, Boston, 1995+Dataquest 2) IC Insights/Ross Assoc.

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21-Mar-00 • 6 • PDF Solutions, Inc.

Missing the Window is Expensive Missing the Window is Expensive

Integration effects market entry point, Integration effects market entry point, performance, and cost basis performance, and cost basis

Annual COGS Savings per 10,000 Wafers1 $0m $100m $200m Top 25% Top 5%

Three costs: Three costs:

Lost market share

Lost market share

Increased NRE

Increased NRE

Increased Costs of

Increased Costs of Goods Sold (COGS) Goods Sold (COGS)

SLIDE 7

21-Mar-00 • 7 • PDF Solutions, Inc.

And Those Yield Loss $$$ are Recoverable ... And Those Yield Loss $$$ are Recoverable ...

Recoverable Yield Loss

0% 25% 50% 75% 100% Mature (.35um) Advanced (.18um) Design Manufacturing Integration Contamination Materials+Other Process Variation

Yield Loss Components

0% 25% 50% 75% 100% Mature (.35um) Advanced (.18um) Design Manufacturing Integration Contamination Materials+Other Process Variation

Bad News: Bad News:

Integration Issues Integration Issues Now Account for 30% Now Account for 30%

f Yield Loss During
f Yield Loss During

Ramp Ramp

Good News: Good News:

Nearly All Integration Nearly All Integration Related Loss is Related Loss is Recoverable Recoverable

SLIDE 8

21-Mar-00 • 8 • PDF Solutions, Inc.

… but, an Integrated Approach is Required … but, an Integrated Approach is Required

Traditional Traditional

Isolated Approach Design Design Design Process Process Process Manufacturing Manufacturing Manufacturing

Holistic Holistic

Manufacturing Manufacturing Manufacturing Process Process Process Design Design Design Integrated Solution

— — Rob Chaplinsky, general partner of Mohr Davidow Ventures

“Ask yourself this: Why does a MIPS core cost 25 cents, and you go to QED and there's a 100-fold increase in value? … the QED part is worth $25 because it is implemented in silicon.”

SLIDE 9

21-Mar-00 • 9 • PDF Solutions, Inc.

Technical Issues Have Both Design and Technical Issues Have Both Design and Manufacturing Implications Manufacturing Implications

New Technology Impact on Design / Manufacturing Interface Compensation Design – Manufacturing Issue Chemical Mechanical Polishing (CMP)

ILD Variability
Depth of focus
Capacitance

variability

Dummy fill
Increased design

margin

What is the circuit

performance impact?

What is the optimal

dummy fill strategy? I-Line @ 0.35µm DuV @ 0.25µm and below

Large w/in chip line

width variation

Optical Proximity

Correction

Printability verification

after OPC?

Gap fill issues?

Channel & Source Drain Engineering RTA, Tox, Poly CD

Increased relative

variability of transistor performance

Statistical design
Increase margins
Traditional worst case

corners not valid Re-use of large design cores

Debugging product

yield issues

Black box yield

models

Fault localization

difficult

SLIDE 10

21-Mar-00 • 10 • PDF Solutions, Inc.

Design or Manufacturing Problem? Design or Manufacturing Problem? Both! Both!

Die X (mm) Die X (mm) Die Y (mm) Die Y (mm) Dielectric thickness (um)

CMP causes layout dependent dielectric variation which causes yield loss Dummy fill improves uniformity But capacitance can go up!

CA CA CB CB (b) CC CD

Optimal solution depends on both design and process considerations

B. Stine et al, Transactions on Electron Devices, Vol 45 No. 3

SLIDE 11

21-Mar-00 • 11 • PDF Solutions, Inc.

Simulating Design - Manufacturing Simulating Design - Manufacturing Integration Integration

Process Recipe Libraries

Design Design Design

Design Analyzer Design Design Analyzer Analyzer Characterization Vehicles Characterization Characterization Vehicles Vehicles Yield Modeler Yield Modeler Yield Modeler Characterization Vehicle Analysis Characterization Characterization Vehicle Analysis Vehicle Analysis

Design Manufacturability Components Manufacturing Models

Yield Impact Matrix Yield Impact Yield Impact Matrix Matrix

Design and Process Improvements Product Design

Manufacturing Manufacturing Manufacturing

SLIDE 12

21-Mar-00 • 12 • PDF Solutions, Inc.

The Yield Impact Matrix The Yield Impact Matrix

Layout Attributes Yield Models IP Layouts Pre-tapeout Product Layouts SRAM Layouts Defect CV Data Layout-Process CV Data Device CV Data

Yield Impact

Overall Chip 85.7% 58.0% 49.8% Block A 95.0% 93.0% 88.4% Block B 95.0% 65.0% 61.8% Virgin Cache 80.0% 80.0% 64.0% Cache w/ Repair 95.0% 96.0% 91.2%

Yield Impact Matrix

Product A Defectivity Design Dependent

SLIDE 13

21-Mar-00 • 13 • PDF Solutions, Inc.

Design Predict Fab Specific Yield

Yes

Design yield issue? Production selection Mask Data Processing fix? Block redesign? Foundry specific yield models

f module

failure rates Feedback to product group Make fix Internal External Shrink Tape out Tape out Redesign Tape out

Yes No No

Using Simulated Integration Results to Make Using Simulated Integration Results to Make Production Decisions Production Decisions

SLIDE 14

21-Mar-00 • 14 • PDF Solutions, Inc.

Example 1: Via Short Flow CV Example Example 1: Via Short Flow CV Example

Floorplan Floorplan

Via2 Loading Contact Loading Isolated Vias Via1 Loading Via2 Misalignment Contact Misalignment Redundancy Size Long Runners Long Runners Long Runners

Via1/Via2/Contact Loading:

Compute yield impact of density.

Via2/Contact Misalignment:

Compute yield impact of misalignment

f via to underlying layers.
Redundancy:

Compare fault rates of single via chains to redundant via chains.

Size:

Compute yield impact of via size. Check process margin.

Long Runners:

Compute yield impact of long metal runs in via chain.

SLIDE 15

21-Mar-00 • 15 • PDF Solutions, Inc.

Example 1: Yield Modeling Example 1: Yield Modeling

Process Specific Via Yield Model Process Specific Via Yield Model

Single Vias Redundancy = 2 Redundancy = 2 Single Vias density density density density

Via Yield Model:

Yvia(non-redundant) = f1(misalignment, density, N) Yvia-redundant) = f2(misalignment, density, N)

SLIDE 16

21-Mar-00 • 16 • PDF Solutions, Inc.

Example 1: Design Yield Entitlement Example 1: Design Yield Entitlement

Product Specific Via Yield Prediction Product Specific Via Yield Prediction

Product B

Via Yield Model:

Yvia(non-redundant) = f1(misalignment, density, N) Yvia-redundant) = f2(misalignment, density, N) Misalignment Data Via-density Product A

Yield Modeler

Via-density Product B

Border Size (um) 0% 20% 40% 60% 80% 100% 0.02 0.04 0.06 0.08 Yield Product A Product B

Product A

SLIDE 17

21-Mar-00 • 17 • PDF Solutions, Inc.

Example 2: Optimizing Fill For Performance Example 2: Optimizing Fill For Performance and Yield and Yield

Questions about dummy fill algorithm:

G Which layers? G What pattern? G Should you exclude sections of the design layout?

Approach

G Build vehicle to characterize performance/yield dependencies on

layout choice

G Build yield models G Optimize dummy fill for product chips

SLIDE 18

21-Mar-00 • 18 • PDF Solutions, Inc.

Example 2: Optimizing Fill for Yield and Example 2: Optimizing Fill for Yield and Performance Performance

30 Identical circuits

G Each contains: SRAM, gate

dependent and interconnect dominated logic circuits, and analog blocks

G Each variant is a DOE element

exploring dummy fill, meta/poly OPC, via sizing options Some fill patterns have positive impact

n yield and

performance for some design blocks

150 160 170 180 190 200 210 220 230 240 250 1 2 3 4 5 Design Blocks Clock Rate A Fill B Fill C Fill