Ring Amplifiers for Switched Capacitor Circuits Benjamin Hershberg 1 - - PowerPoint PPT Presentation

Ring Amplifiers for Switched Capacitor Circuits

Benjamin Hershberg1, Skyler Weaver1, Kazuki Sobue2, Seiji Takeuchi2, Koichi Hamashita2, Un-Ku Moon1

1Oregon State University, Corvallis, OR, USA 2Asahi Kasei Microdevices, Atsugi, Japan

A/D Scaling Trends: FoM1

• Performance continues to scale well with process
• FoM1 best describes low/medium-resolution A/D performance

[Jonsson, NORCHIP 2010]

2

A/D Scaling Trends: FoM2

[Jonsson, NORCHIP 2010]

• FoM2 best describes high-resolution A/D performance
• Noise floor degrades faster than power/speed improves.

3

Beating the Trend

We need amplifiers that are:

• Immune to SNR loss from low-voltage, degrading ro
• Exploit digital scaling benefits
• Avoid conventional RC-based settling

4

Beating the Trend

• VDZ

+ VIN VOUT

Ring Amplifier

(Ring Amp, RAMP)

5

Ring Amplification Basic Theory

Ring Amplifier: Basic Theory

• Basic MDAC test structure

RST

VCMX VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

AMP

7

Ring Amplifier: Basic Theory

• Ring Oscillator
• Unstable…

…but will oscillate around the correct settled value

RST

VCMX=0.6V VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

VIN VOUT

RST

8

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Ring Oscillator Sample Waveform

VCMX = 0.6V (ideal settled input value)

VIN

9

Ring Amplifier: Basic Theory

RST

VCMX VIN ±VREF CLOAD

RST RST

VCMO

Example MDAC Feedback Structure

• VDZ

+

RST RST RST

• VOS+

+VOS-

• Split signal into two separate paths
• Embed offset in each path

10

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

11

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

12

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

13

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 0mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

14

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 200mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

15

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 200mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Plateaus form at dead-zone crossings

16

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

17

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 300mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

18

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 350mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

19

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 400mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

20

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

Decreasing VOV reduces slew-rate

21

VOV Dynamic Pinch-off

22

AV2*(VIN*AV1 + VOS) AV2*(VIN*AV1 - VOS)

• VDZ

+ VIN VOUT

AV1 AV2

+VOS-

• VOS+

VOV Dynamic Pinch-off

AV2*(VIN*AV1 + VOS) AV2*(VIN*AV1 - VOS)

• VDZ

+ VIN VOUT

AV1 AV2

+VOS-

• VOS+

VMIN > VSS? → Pinchoff! VMAX < VDD? → Pinchoff!

23

– ID decreases

• VOV → ID

2

– Ro increases

• Dominant pole → DC

Ring Amplifier Core Benefits

Slew-based charging

• Charges with maximally biased, digitally-switched

current sources

– VOV = VDD – Can be very small, even for large CLOAD – Decouples internal speed vs. output load requirements

Exponential dynamic stabilization

• Very fast
• Well defined tradeoffs

24

Ring Amplifier Core Benefits

Scalability (Speed/Power)

• Internal speed/power (mostly) independent of CLOAD

– Inverter td, crowbar current, parasitic C’s – Digital power-delay product scaling benefits apply

• Power/speed product scales with digital process trends

td VDD IAVG PDP = VDD·IAVG·td = Etot DIN DOUT CGS

25

Ring Amplifier Core Benefits

Scalability (Output Swing / SNR)

• Compression immune: rail-to-rail output swing

– 50dB: Input-referred dead-zone size will limit accuracy – 90dB: dynamic pinch-off effects maintain high accuracy – VOV pinchoff: decreases VDSAT, decreses ID, increases ro

1 2 3 4 5 6 7 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Volts time (ns) Small Swing Medium Swing Large Swing 1 2 3 4 5 6 7 0.55 0.6 0.65 Volts time (ns) Small Swing Medium Swing Large Swing

26

ADC Implementation Details

Split-CLS (Correlated Level Shifting)

• Split-CLS

– Generalized form of Correlated Level Shifting (CLS)

CCLS VOUT

ФS ФA

VIN

ФA

VCMO

ФS

(+/-Vr,0)

AΦ1 AΦ2

Vx VCLS

AMP1 AMP2

VCMO

ФS

[Hershberg, ISSCC 2010]

28

Split-CLS (Correlated Level Shifting)

CCLS VOUT

ФS ФA

VIN

ФA

VCMO

ФS

(+/-Vr,0)

AΦ1 AΦ2

Vx VCLS

AMP1 AMP2

VCMO

ФS

Ф1:

• amp charges output

directly

• processes full signal

Amplifier Design Requirements Ф1 Ф2 Output Swing Large Small Slew Rate Large Small

29

Split-CLS (Correlated Level Shifting)

CCLS VOUT

ФS ФA

VIN

ФA

VCMO

ФS

(+/-Vr,0)

AΦ1 AΦ2

Vx VCLS

AMP1 AMP2

VCMO

ФS

Ф2:

• opamp is level-shifted

to mid-rail

• processes error only

Amplifier Design Requirements Ф1 Ф2 Output Swing Large Small Slew Rate Large Small

30

Split-CLS (Correlated Level Shifting)

• Optimized design for each phase

– Increase overall accuracy & efficiency

• This design:

– Ф1: Ring Amp – Ф2: Telescopic opamp

• Finite opamp gain error becomes approx. 1 / (A1*A2)

55dB ring amp + 65dB opamp 120dB effective gain

31

Pipelined ADC Overview

3b

CU = 200 fF

3b

CU = 100 fF

3b

CU = 50 fF

Uses Split-CLS: Ring Amp + Telescopic Opamp Uses Ring Amp Only

3b

CU = 50 fF

3b

CU = 50 fF

3b

CU = 50 fF

3b

FLASH

VIN+

includes 16CU total (differential) dummy load

VIN-

3b: 2b + 1b redundancy (MDAC gain of 4 per stage)

32

Pipelined ADC Stage 1 MDAC

±VREF

VIN+ VO+

ΦSE ΦS ΦA

RAMP

VCMX

CU

CLR

±VREF

VIN+

ΦS CU

VCMO VOTA_CM

2CU

CLR

±VREF

VIN- VO-

ΦSE ΦS ΦA

RAMP

CU

CLR

±VREF

VIN-

ΦS x6 (8 total) CU

VCMO

2CU

CLR

CCLS

ΦSE ΦSE ΦCLS ΦA ΦA

OTA

x6 (8 total)

CCLS

33

Pipelined ADC Stage 2-4 MDAC

±VREF

VIN+ VO+

ΦS ΦA

RAMP

CU ±VREF

VIN+

ΦS CU

VCMO VOTA_CM

2CU ±VREF

VIN- VO-

ΦSE ΦS ΦA

RAMP

CU ±VREF

VIN-

ΦS x6 (8 total) CU

VCMO

2CU

CCLS

ΦSE ΦSE ΦCLS ΦA ΦA

OTA

x6 (8 total)

CCLS

ΦSE

VCMX

ΦSE ΦA ΦA 34

Pipelined ADC Stage 5-6 MDAC

±VREF

VIN+ VO+

ΦS ΦA

RAMP

CU ±VREF

VIN+

ΦS CU

VCMO

2CU ±VREF

VIN- VO-

ΦSE ΦS ΦA

RAMP

CU ±VREF

VIN-

ΦS x6 (8 total) CU

VCMO

2CU ΦSE ΦSE ΦA ΦA x6 (8 total) ΦSE

VCMX

ΦSE ΦA ΦA 35

Ring Amplifier Core Structure

VIN+ VOUT+ VRP

REFRESH REFRESH

VRN

REFRESH

• No need to refresh every cycle.
• Can disable ring amp when not in use

36

VIN+ VOUT+ VRP

FRONT ENABLE REFRESH REFRESH

VRN

REFRESH ENABLE ENABLE ENABLE ENABLE

Ring Amplifier Power Save Feature

• Only enable when amplifying or refreshing
• Refresh only once every N cycles (during ФS)

37

Ring Amplifier CMFB

VIN+ VOUT+ VRP

FRONT ENABLE REFRESH REFRESH

VRN

REFRESH ENABLE ENABLE ENABLE ENABLE

VCMO

CMFB network

Identical ring amp for negative MDAC path

REFRESH

38

Float-Biased Switched Opamp

• Bias network isolation
• Fast startup

Bias Network

39

Float-Biased Switched Opamp

Bias Network

Incremental bias voltage sampled Voltage Kickback Correct bias charge trapped

40

Float-Biased Switched Opamp

Bias Network

Bias charge refreshed No Voltage Kickback

41

Measurement Results

Input Spectrum

43

Performance vs. Input Frequency

60 65 70 75 80 85 90 95 100 2 4 6 8 10 dB Input Frequency (MHz) SNDR SNR SFDR ERBW > 10 MHz

44

SNDR vs. Input Amplitude

40 45 50 55 60 65 70 75 80

• 35.00
• 30.00
• 25.00
• 20.00
• 15.00
• 10.00
• 5.00

0.00 SNDR (dB) Vin (dBFS)

VDDA = 1.3V VFS = 2.5V pk-pk diff

45

Ring Amp Dead-Zone Sensitivity

64 66 68 70 72 74 76 78

• 100
• 50

50 100 SNDR (dB) 1st stage dead-zone (mV differential pk-pk)

46

Ring Amp Supply Sensitivity

64 66 68 70 72 74 76 78 1150 1200 1250 1300 1350 1400 1450 1500 SNDR (dB) Supply Voltage (mV) Vrefp = 1275mV

47

Opamp Float-Bias Switching

• Reduces total opamp power by 35%:
• Bias network isolation improves accuracy by 0.6dB:

1769uA 1151uA 76.2dB 76.8dB

48

Performance Summary

Technology 0.18µm 1P4M CMOS Resolution 15 bits Analog Supply 1.3 V Sampling rate 20 Msps ERBW 10 MHz Input Range 2.5 V pk-pk diff. SNDR 76.8 dB SNR 77.2 dB SFDR 95.4 dB ENOB 12.5 bits Total Power 5.1 mW FoM 45 fJ/c-step

49

1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07 10 20 30 40 50 60 70 80 90 100 110 120

P/fs [pJ] SNDR [dB]

ISSCC 2011 VLSI 2011 ISSCC 1997-2010 VLSI 1997-2010 This Work FOM=100fJ/conv-step FOM=10fJ/conv-step

This Work

Best power efficiency of any high-resolution ADC ever reported (nyquist or oversampling)

[B. Murmann, 2011]

50

Conclusion

• Ring Amplification

– High efficiency slew-based charging – Rail-to-rail output swing – Performance scales with digital process

• Split-CLS

– Efficient coarse charging – Very accurate fine settling – High-efficiency, high accuracy amplification

51

Thank you for your attention

Additional Slides

Possibly useful in Q&A afterwards

Systematic dead-zone offset

60 64 68 72 76 80

• 100
• 80
• 60
• 40
• 20

20 40 60 80 100 SNDR (dB) 1st Stage Deadzone (mV pk-pk differential)

1st Stage Deadzone vs SNDR

Chip 1 Chip 2 + 1.3dB

54

Ring Amp Accuracy

• Determined using 2 independent test approaches
• Ring Amps contribute ~55dB to overall accuracy

30 35 40 45 50 55 60 3 5 7 9 11 13 15 17 SNDR

• approx. RAMP operation time window

(ns)

SNDR vs. Ring Amp Timing (with opamps off)

20 40 60 80 100 10 30 50 70 90 SNDR (dB) fs (MHz)

Peak SNDR vs. Sampling Frequency

~55dB plateau

Test method 1:

Increase fs until opamps don’t have enough time to turn on.

Test method 2:

Power down opamps, and adjust the time the ring amps are allowed to settle.

~55dB plateau

55

Input-cap clearing

• FFT spectrum when the input capacitors aren’t cleared before being

re-connected to the chip signal input:

56

More about Compression Immunity

• Isn’t this just a 90dB amplifier that’s been limited by the

dead-zone size to look like a 60dB amplifier?

– Answer: No!

• With a well chosen dead-zone value:

– Current pinches off, increasing ro – VOV shrinks, decreasing VDSAT – High gain preserved, even when VDS is very small

• Depends on dead-zone value?

– Yes, but doesn’t actually matter… – Small dead-zone: compression immune – Large dead-zone: some compression (lower accuracy anyway)

57

Power Breakdown

58

DNL - INL

1000 2000 3000 4000 5000 6000 7000 8000

• 0.5

0.5 DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE DNL (LSB for 13b) 1000 2000 3000 4000 5000 6000 7000 8000

• 2
• 1

1 2 INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE DIGITAL OUTPUT CODE INL(LSB for 13b)

59

Supply current vs. Stage 1 DZ

800 850 900 950

• 300
• 200
• 100

100 200 300 Global Ring Amp Current (uA) Deadzone (mV pk-pk differential)

60

A/D Scaling Trends: FoM2

[Jonsson, NORCHIP 2010]

• FoM2 best describes high-resolution A/D performance
• Noise floor degrades faster than power/speed improves.

1995 2000 2005

61

Chip Micrograph

Full die micrograph Stage 1 MDAC

62

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns)

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

63

1 2 3 4 5 6 0.2 0.4 0.6 0.8 1 1.2 Volts time (ns)

Ring Amplifier Sample Waveform

VDEADZONE = 250mV

1.2 1 0.8 0.6 0.4 0.2 1 2 3 4 5 6

Volts time (ns) 1) Dead-zone shifts input

• f stg2 closer to threshold

2) Finite gain of stg2 causes VOV to desaturate 3) Output current pinches off, locks into dead-zone

64

• VDZ

+ VAN VIN VOUT VA VBP VBN VAP

Ring Amp Power-Save Feature

1 2 3 4 5 20 40 60 Ring Amp Supply Current (mA) Skip Cycles per Refresh Cycle

65