Roll-to-roll manufacture of organic transistors for low cost - - PowerPoint PPT Presentation

1 21st Sept 2011 1

Roll-to-roll manufacture of organic transistors for low cost circuits

Hazel Assender Dr Gamal Abbas, Ziqian Ding

Department of Materials University of Oxford

DALMATIAN

TECHNOLOGY

2 21st Sept 2011 2

Acknowledgements

Bangor

Prof Martin Taylor Aled Williams Eifion Patchett

Oxford

Dr Kanad Mallik

Leeds

Prof Long Lin Dr Weidong He

Manchester

Prof Steve Yeates Dr John Morrison

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Flagship project

Can we manufacture transistors/simple circuits from organic materials using R2R vacuum evaporation processes?

Need to consider: 1) Process parameters in R2R environment – building and

testing transistors 2) Circuit design tailored for the properties achievable with this manufacturing route 3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route 4) Patterning processes 5) Robustness of final devices

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Roll-to-roll processing

Oxford vacuum web coater Webspeed up to 5 ms-1 Web width 350 mm

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The story so far…….

5

Substrate (e.g. PET) Insulator (acrylic) Gate Possible interlayer

• Org. Semiconductor

Source and Drain (Metal) L W

• 5
• 40
• 30
• 20
• 10

V

S-D (V)

I

S-D

(nA)

0V

• 10V
• 20V
• 30V
• 40V
• 10

Possible surface modification

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Materials developments

• Moved from glass to PEN substrates

S S Pentacenes DiNapthoThienoThiophene DNTT

• Moved from Au to Al gate electrode
• New masks: shorter S/D length,

multiple transistors

• Tried new semiconductor, DNTT

Anticipated better stability Still high mobility

• Tried insulator acrylate with higher

permittivity

Thinner layer deposition More polarizable

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Depositing the insulator

• In-line process
• High speed

i. Evaporate monomer (liquid) ii. Condenses onto substrate (web) as a liquid (flat) iii. Polymerize (cure) in-situ

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E-beam cure

• FTIR indicates ‘full’ cure
• IV curves of e-beam cured device
• Poor saturation, greater hysteresis, poor stability

8

You can ‘solve’ these issues by annealing

• Anneal at 150 C for 1 hour

NB At a web speed of 50m/min, this annealing time requires a web path length of 3km! Ion/Ioff = 1.3x103 Vth = 10V µ = 0.1cm2/Vs

• 40
• 30
• 20
• 10
• 10V
• 20V
• 30V
• 40V

VD(V)

I

D (A)

ID(µA)

• 2
• 4
• 6
• 60
• 40
• 20

20

10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

960nm @ V D =-60V 425 nm @V D =-40V I

D

(A)

VG(V)

100 10 1 0.001 0.01 0.1

ID(µA)

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Plasma cure

• Cures in a single pass of the plasma as the polymer is

deposited

(although several passes of deposition are made for small-scale experiments) Plasma-cured TRPGDA E-beam-cured TRPGDA

• 40
• 20

20 1 2 3 4 0.001 0.01 0.1 1.0 10 100 0.01 0.1 1 10 100

(ID)1/2(µA1/2)

ID(mA) VG(V)

• 30V

VG(V)

(ID)1/2(µA1/2)

• 40
• 20

20 1 2 3 4 5 Ion/Ioff=1.1x103 Ion/Ioff=3.2x103

• 30V- drak

ID(mA)

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Device Lifetimes

OFETs with plasma-cured dielectric show a reasonably stable performance in air over 10 cycles

• 40
• 20

20

1 2

• 50 -40 -30 -20 -10 0
• 3.0
• 2.0
• 1.0

0.0 10

• 3

10

• 2

10

• 1

1 10 (I

D

)

1/2

(µA

1/2

) ID(µA) V

D

(V)

• 10V
• 20V
• 30V
• 40V
• 50V

I

D

(µA)

1st scan 10th scan

V

G

(V)

V d =-50V I

• n

/I

• ff =2.1X10

3

5 10 15 20 25 30 (005) (004) (003) (002)

Intensity (a.u)

2 θ (degrees) (001)

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Shelf-life stability

1st Week 15th Week Ion/Ioff 2.0x103 1.8x102 Vth (V) 10

• 13

µ (cm2/Vs) 0.1 0.07

• 60
• 40
• 20

20 10-5 10-6 10-7 10-8 10-9

• 60
• 40
• 20

20 40 1 2 3 4 0.0 0.5 1.0 1.5

ID(A)

1st week

V

G

(V) 15-weeks (I

D

)

1/2

(µA)

1/2

(I

D

)

1/2

(µA)

1/2

V

G

(V) 1st week

15 weeks

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Interfacial modification

• Self-assembled monolayers are required in printed
• rganic transistors
• Modify the insulator surface to become more

hydrophobic

• A hydrophobic (PS) layer gives improved pentacene

morphology & devices

Less effect is seen with fresh pentacene material without PS with PS

10 20 30

Scale: 1µm =

with PS without PS

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Surface modification

13

Improved pentacene morphology gives better devices Greater mobility, lower off-current

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Testing in Vacuum

• See a lower off-current and higher mobility
• Investigate encapsulation methods

Device Performance (devices with PS layer characterised in vacuum)

• Ion/Ioff up to 107, Mobility ≥ 0.4cm2/Vs
• Very small operational degradation at moderate voltage

Transfer and IV curves of pentacene on SB3 dielectric on PEN substrate

• 12
• 24
• 36

Id(µA)

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Device encapsulation

• Well-established vacuum deposition methods for gas barrier layers
• Used for food packaging
• e.g. acrylate insulator/smoothing layer followed by Al or AlOx
• Could be fully-integrated into the process

Substrate (PEN) Insulator (acrylic) PS interlayer Al, acrylate barrier layer Source and Drain (Au)

Gate (Al)

DNTT or pentacene

L W

Al, acrylate barrier layer

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Progress so far…..

1) Process parameters in R2R environment – building and testing transistors

Shorter S/D length Plastic substrates Al gate electrode Improved curing method Surface modification layer Hysteresis measurements In-vacuum testing

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Progress so far……

2) Circuit design tailored for the properties achievable with this manufacturing route

Transistor modelling underway based on device measurements

3) Materials (semiconductor and gate insulator layer) developed for this manufacturing route

New SC synthesised, more under development Tried new insulator material

4) Patterning processes

Favoured options for SC and insulator layers under development

5) Robustness of final devices

Planning encapsulation experiments