SCRAM Instructions
Philipp Koehn 16 September 2019
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
SCRAM Instructions Philipp Koehn 16 September 2019 Philipp Koehn - - PowerPoint PPT Presentation
SCRAM Instructions Philipp Koehn 16 September 2019 Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019 Reminder 1 Fully work through a computer circuit assembly code Simple but Complete Random
Philipp Koehn 16 September 2019
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– circuit – assembly code
– every instruction is 8 bit – 4 bit for op-code: 9 different operations (of 16 possible) – 4 bit for address: 16 bytes of memory
– The Random Access Machine – The SCRAM
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Time Command t0 MAR ← PC t1 MBR ← M, PC ← PC + 1 t2 IR ← MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q1 t3 MAR ← IR(D) q1 t4 MBR ← M q1 t5 AC ← MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Accumulator receives value from memory buffer (MBR)
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Memory address comes from data field of instruction
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Selector picks between inputs
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q1 t3 MAR ← IR(D) q1 t4 MBR ← M q1 t5 AC ← MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
– Instruction op code Q – Time step in micro program T
– signals to register transfer – signals to selectors
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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q1 t3 MAR ← IR(D)
– MAR write flag set – MAR’s selector to input IR(D)
DI DO W A
16x8 RAM MAR
W
PC
W INC
IR
W C D
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S x1 x2
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Decoder Decoder
x1 x2 q1 t5 to selectior to MAR write Micro instruction: q1 AND t5: MAR ← IR(D)
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Decoder Decoder
x1 x2 q1 t5
AND
to selectior to MAR write Micro instruction: q1 AND t5: MAR ← IR(D)
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Decoder Decoder
x1 x2 q1 t5
AND
to selectior to MAR write
OR
Micro instruction: q1 AND t5: MAR ← IR(D) Set signal to MAR write flag
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Decoder Decoder
x1 x2 q1 t5
AND
to selectior to MAR write
OR OR
Micro instruction: q1 AND t5: MAR ← IR(D) Set appropriate value to MAR selector
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Decoder Decoder
x1 x2 q1 t5
AND
to selectior to MAR write
OR OR OR
Micro instruction: q1 AND t5: MAR ← IR(D) Increase micro program time step
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Control logic is a large matrix t0 t1 t2 t3 t4 t5 t6 t7 t8 q0 * * * * * * * * * q1 * * * * * * * * * q2 * * * * * * * * * q3 * * * * * * * * * q4 * * * * * * * * * q5 * * * * * * * * * q6 * * * * * * * * * q7 * * * * * * * * * q8 * * * * * * * * *
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Control logic is a large matrix t0 t1 t2 t3 t4 t5 t6 t7 t8 q0 * * * * * * * * * q1 * * * * * * * * * q2 * * * * * * * * * q3 * * * * * * * * * q4 * * * * * * * * * q5 * * * * * * * * * q6 * * * * * * * * * q7 * * * * * * * * * q8 * * * * * * * * *
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Control logic is a large matrix t0 t1 t2 t3 t4 t5 t6 t7 t8 q0 * * * * * * * * * q1 * * * * * x1x2t * * * q2 * * * * * * * * * q3 * * * * * * * * * q4 * * * * * * * * * q5 * * * * * * * * * q6 * * * * * * * * * q7 * * * * * * * * * q8 * * * * * * * * *
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– load value of specified memory address – use that value as a memory address (second lookup) – store value from second lookup into accumulator
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q2 t3 MAR ← IR(D) q2 t4 MBR ← M q2 t5 MAR ← MBR q2 t6 MBR ← M q2 t7 AC ← MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q3 t3 MAR ← IR(D) q3 t4 M ← AC
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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D I DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– load value of specified memory address – use that value as a memory address (second lookup) – store value from accumulator to that address
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q4 t3 MAR ← IR(D) q4 t4 MBR ← M q4 t3 MAR ← MBR q4 t4 M ← AC
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S DI
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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D I DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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S=A+B
S=A-B
set if result of operation is 0
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– load value of specified memory address – use that value as input to arithmetic logic unit – store output from arithmetic logic unit into accumulator
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q5 t3 MAR ← IR(D) q5 t4 MBR ← M q5 t5 AC ← AC + MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
60
Op Code Time Command q5 t3 MAR ← IR(D) q5 t4 MBR ← M q5 t5 AC ← AC - MBR
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Time Command t0 MAR ← PC t1 MBR ← M t2 IR ← MBR ⇒ t3 PC ← PC + 1
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– instruction fetch (includes program counter inc) – command-specific micro instructions
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Op Code Time Command q7 t3 PC ← IR(D)
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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– set when result of a ALU operation is 0 – stored in flag
ALU
A B S CO CI Z SUB
Z
W
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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DI DO W A
16x8 RAM MAR MBR
W W
PC
W INC
IR
W
Decoder Control Logic Unit
C D
T
INC
Decoder
CLEAR
NOT
Q T
Selector
S
ALU
A B S CO CI Z SUB
AC
W
Selector
S
Z
W
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019
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(same as JMP) Zero Op Code Time Command 1 q7 t3 PC ← IR(D)
Philipp Koehn Computer Systems Fundamentals: SCRAM Instructions 16 September 2019