SOI and Related Activities in AGH-UST and IFJ PAN (1) Sebastian Gb , - - PowerPoint PPT Presentation

SOI and Related Activities in AGH-UST and IFJ PAN

(1) Sebastian Głąb, M.I. Ahmed, Mateusz Baszczyk, Szymon Bugiel, Piotr Dorosz, Roma Dasgupta, Marek Idzik, Wojciech Kucewicz, Jakub Moroń, Maria Sapor (2) Piotr Kapusta, Michał Turała

(1) AGH University of Science and Technology,

• A. Mickiewicza 30, 30-059 Krakow, Poland

(2) Institute of Nuclear Physics Polish Academy of Sciences, Radzikowskiego 152, 31-342 Krakow, Poland Email: sglab@agh.edu.pl

Agenda

• Presentation of AGH University of Science and Technology;
• General description of submitted chips;
• First matrix of pixels;
• Second matrix of pixels;
• Third and fourth matrix of pixels;
• Successive Approximation Register Analog-to-Digital Converter;
• Bandgap voltage reference with temperature sensor;
• Synthesizable digital library.

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AGH UST history

In 1913, Emperor Francis Joseph approved the establishment of a higher school of mining in Krakow. In 1919, Józef Piłsudski, the Head

• f the State, inaugurated the

Academy of Mining. In 1947, an internal resolution was adopted to change the name to the Academy of Mining and Metallurgy.

www.agh.edu.pl

Facts and figures

• 16 faculties
• 57 fields of study
• more than 200 specialisations
• total number of students: 32,245
• full-time students: 26,314
• part-time students: 5,931
• doctoral students: 1002
• postgraduate students: 2284
• over 170,000 graduates
• over 2,000 researchers including

560 independent research workers

www.agh.edu.pl

Results of scientific research activity

• International projects – nearly 200
• Domestic projects – over 2,000
• Research and innovation:
• obtained patents – 93
• patent pending innovations – 112
• Licences:
• licence agreements – 39

Publications 5871 Books 141 Chapters in books 479 Articles in magazines 2547 Reports and papers 2425

www.agh.edu.pl

Research and laboratories

The latest generation analytical electron microscope (S)TEM FEI Titan Cubed G-2 60-300 The supercomputer “Zeus” - classified among 100 most powerful computers in the world

www.agh.edu.pl

Centre of Computer Science

Infrastructure

Faculty of Energy and Fuels Centre of Ceramics Academic Centre of Materials and Nanotechnology

www.agh.edu.pl

Description of submitted chips

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SOI chips ps submit itted ed by AGH H & IFJ

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Chip no. 1 (submitted in July 2012): a) One matrix of pixels 32x32 (two layouts: small and large BPW); b) two asynchronous, dynamic logic, 10 bit SAR ADCs; c) bandgap voltage reference and temperature sensor (ver. 1 and ver. 2).

SOI chips ps submit itted ed by AGH H & IFJ, cont.

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Chip no. 2 (submitted in July 2013): a) matrix of pixels 32x32 (two layouts: small and noBPW); b) digital library test structures; c) bandgap voltage reference and temperature sensor (ver. 2b and ver. 3); d) history effect test circuit; e) bare test pixels; f) bandgap diodes test structures; g) SOI2 strip.

SOI chips ps submit itted ed by AGH H & IFJ, cont.

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Chip no. 3 (submitted in July 2014): a) matrix of pixels 16x32 (charge amplifier; small and large BPW); b) matrix of pixels 16x32 (charge amplifier, shaper, peak detector); c) Two asynchronous, static logic, 10 bit SAR ADC; d) bandgap voltage reference and temperature sensor (ver. 4 and ver. 4b).

Next MPW submis issi sion

• n plans

ns

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Chip no. 4 (?April 2015?): a) matrix of self addressing pixels; b) matrix of pixels with Time Over Threshold; c) Improved 10 bit SAR ADC; d) 6 bit, column SAR ADC; e) bandgap voltage reference and temperature sensor (to be decided).

Pixel matrices

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First versi sion

• n of p

pixel

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Designed by Piotr Kapusta

First versi sion

• n of p

pixel, , cont nt.

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Laid by Piotr Kapusta Laid by Sebastian Głąb

SMALL LARGE

First versi sion

• n of p

pixel, l, cont nt.

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• The measured ENC value was found to be about 115 electrons at 60 V bias and 82

μs integration time (in which 56 e came from the leakage current, 34 e from the input transistor and the rest, i.e. 94 electrons is produced in the readout electronics (including out of chip components).

• The chip operates in the “rolling shutter” mode, the dead time equals 2.7%.
• The calculated gain is 9.3ADC units/eV, with non-linearity better than 2.6ADC units.

Total Equivalent Noise Charge vs detector bias. Integration time = 90 μs.

First versi sion

• n of p

pixel, l, cont nt.

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Am241 spectra from different sensor areas.

• M. I. Ahmed, S. Głąb, M. Idzik, P. J. Kapusta, M. Turała, Prototype pixel detector in the SOI technology,

Journal of Instrumentation; ISSN 1748-0221. - 2014 vol. 9 no. 2, s. 1–8 article no. C02010. http://iopscience.iop.org/1748-0221/9/02/C02010

Second

• nd versi

sion

• n of pixel matrix

ix

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• Circuit schematics same as in first version;
• Added SOI2 layer to all pixels;
• Large pixels substituted by pixels without BPW area;
• One bug fixed (BPW line shorted with bias line);
• Broken output amplifier – matrix can not be read…

Third ird version ion of p pixel

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Designed by Szymon Bugiel

A telescope cascode with an additional current source for higher

• utput resistance.

Two different gains. Correlated double sampling.

New Column mn Amplifier ier

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Designed by Szymon Bugiel

Third ird version ion of p pixel, l, summary mary

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• The new pixels use newly designed frontend electronics in the charge amplifier

configuration, in order to obtain significantly lower noise level than in the first prototype.

• Thanks to use of recycling folded cascode as the column amplifiers a significant

reduction of the power consumption should be possible.

• Two separate SOI2 areas; one below all PMOS transistors, second one under all

NMOS transistors. Possibility to study compensation of radiation damage effects.

• Two layouts of pixels: half of the pixels were drawn using standard BPW/BNW

layer and other half without it. Possibility to study effectiveness of SOI2 shielding.

Szymon Bugiel, Roma Dasgupta, Sebastian Głąb, Marek Idzik, Piotr Kapusta, Development of pixel detector in novel sub-micron technology SOI CMOS 200 nm, MIXDES 2014; proceedings of the 21st international conference; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872186

Fourth rth vers rsion ion of pixel

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Designed by Piotr Kapusta Details are unknown…

3rd and 4th pixel layout

• uts comparis

arison

• n

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Designed by Piotr Kapusta Designed by Szymon Bugiel

Successive Approximation Register Analog-to-Digital converter

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10 bit SAR ADC

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Designed by Roma Dasgupta

10 bit SAR ADC, cont. t.

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Designed by Roma Dasgupta Schematics of designed DAC

10 bit SAR ADC, cont. t.

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Designed by Roma Dasgupta

10 bit SAR ADC, cont. t.

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• 10 bit resolution, 20 MSps at a power consumption of about 900 μW.
• Zero static power dissipation.
• The differential, segmented DAC with merge capacitor switching (MCS) scheme.
• The MCS scheme achieves 93.4% less switching energy as compared to the

conventional SAR architecture.

• Layout size is about 200 μm × 300 μm.

Roma Dasgupta, Szymon Bugiel, Sebastian Głąb, Marek Idzik, Jakub Moroń, Piotr Kapusta, Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS, MIXDES 2014; proceedings of the 21st international conference; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6872180

The dynamic parameters of designed SAR ADC

Bandgap Voltage Reference and Temperature Sensor

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Positive ive temperature rature coefficien ficient (PTC TC)

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It was recognized in 1964 that if two bipolar transistors operate at unequal current densities, then the difference between their base-emitter voltages is directly proportional to the absolute temperature.

K mV T Vth 087 .    

   

m n q kT m n V V

th BE

     ln ln

Negative ive temperature rature coefficie icient nt (NTC TC)

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Forward voltage of p-n junction VBE has negative temperature coefficient.

 

T q E V m V T V

g th BE BE

/ 4       2 3   m eV Eg 12 . 1  q kT Vth 

With VBE = 750 mV, T = 300 K:

K mV T VBE 5 . 1    

Temperature exponent of mobility: Thermal voltage: Bandgap energy of silicon:

Schemat hematic ic of t the circu cuit it

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Layout

• ut of the circuit

cuit

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Version 1 and 2 based on „cold” and „hot” diode model respectively. 267 μm x 124 μm (submitted in July 2012) Version 2 with improved layout and version 3. 298 μm x 185 μm (submitted in July 2013) Version 4. 240 μm x 157 μm (submitted in January 2014) Not yet available.

Bandgap („hot” diode model)

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The simulations were done for temperature range from -10 °C to +130 °C showing very good temperature sensor linearity and stable (within 1 mV) bandgap voltage output in the whole range.

Measure urements ments of P PTAT

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Substrate type Sensitivity [mV/K] Smallest Average Largest RMS CZN 2.877 3.055 3.241 0.111 FZN 2.771 2.867 3.028 0.081 FZP 2.457 2.648 2.922 0.164

All temperature sensors were designed so as to have sensitivity of about 3.5 mV/K. Chips will be measured in environmental chamber here in KEK.

Measure urements ments of b bandgap gap

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Due to moderate accuracy of diode models included in design kit, measurements results for version 1 and 2 are much worse that simulation results.

Circuit version Sensitivity [μV/K] Smallest Average Largest RMS Version 1

• 498

Version 2

• 277
• 357
• 516

69 Version 3

• 21
• 101
• 258

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Measure urements ments of b bandgap gap (vers ersion ion 3 only) y)

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Circuits fabricated

• n CZN substrate

have satisfactory behavior with temperature. Whereas circuits fabricated on newly introduced substrates FZN and FZP exhibit clearly worse performance. This phenomena must be consulted with substrates foundry.

Substrate type Sensitivity [μV/K] Smallest Average Largest RMS CZN

• 21
• 35
• 52

13 FZN

• 54
• 78
• 90

17 FZP

• 123
• 191
• 258

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Bandg dgap ap voltag age e source ce and temperature erature sensor,

• r,

summary mary

• A temperature sensor and bandgap voltage reference source were designed and

produced in novel submicron 200 nm SOI technology comprising electronics and sensor layers.

• A satisfactory operation of both circuits was verified in a wide temperature range.
• The temperature sensor shows sensitivity of about 3 mV/K which is consistent with

simulations.

• Subsequent versions of the bandgap voltage reference show major improvements

suggesting that modification of diode model would be desirable.

• Both circuits exhibit similar degradation of performance for substrates other than
• CZN. This needs further studies because higher resistivity FZP and FZN floating zone

substrates are more desirable for production of radiation detectors.

• S. Głąb, M. Baszczyk, P. Dorosz, M. Idzik, W. Kucewicz, M. Sapor, P. Kapusta, Y. Arai, T. Miyoshi, A. Takeda, Bandgap Voltage Reference and

Temperature Sensor in Novel SOI Technology, ICSES 2014; proceedings of the International Conference on Signals and Electronics; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6948708

Synthesizable Digital Library

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Motiva vatio tion

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Manually placed logic Synthetized logic

Digital al libra rary ry

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Digital Library contains 93 elements:

• Half adders and full adders (ADD21, ADD22, ADD31, ADD32);
• And-Or-Invert (AOI210, AOI211, AOI220, AOI221, AOI310, AOI311, AOI2110, AOI2111);
• Basic logic gates with 2 or 3 inputs (AND20, AND21, AND22, AND30, NAND20, NAND30, NOR20,

NOR30, OR20, OR21, XNR20, XOR20);

• Clock buffer, tri-state buffers, buffers with enable input (CLKBU2, BUFT2, BUFT3, BUFE2,

BUFE3, BUF2, BUF3, BUF4, BUF5, BUF7);

• Bus holder (BUSHD);
• D-type flip-flops with asynchronous clear, preset, chip enable (DF1, DF2, DFC1, DFC2,

DFCP1, DFCP2, DFP1, DFP2, DFE1, DFEC1, DFECP1, DFEP1);

• T-type flip-flops with asynchronous clear, preset, chip enable (TFC1, TFC2, TFCP1, TFCP2,

TFP1, TFP2, TFEC1, TFECP1, TFEP1);

• Glue cells (FILL1, FILL2, FILL4, FILL8);
• Inverters (CLKIN0, INV0, INV1, INV2, INV4, INV5, INV6, INV7, INV8, INV9);
• Constant logic level source (LOGIC0, LOGIC1);
• D-type latches with asynchronous clear and preset (DL1, DL2, DLC1, DLC2, DLCP1, DLCP2,

DLCPQ1, DLCPQ2, DLCQ1, DLCQ2, DLP1, DLP2, DLPQ1, DLPQ2, DLQ1, DLQ2);

• Multiplexers (IMUX20, IMUX30, IMUX40, MUX20, MUX30).

Design n assumpti mptions

• ns

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• Elements are optimized in terms of area;
• All internal wiring drawn on polysilicon and first metal layers;
• Height of 7.68 µm was chosen for all layout cells.

Layout of D-type flip-flop with asynchronous clear and preset

Design n assumpti mptions

• ns cont’d

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• Minimal transistor’s channel length of

0.2 µm was used in all transistors;

• NMOS channel width is set to 0.5 μm

(minimum size in this technology);

• PMOS channel width is set to 1.2 μm;
• This channel width ratio (i.e. 1:2.4)

ensures the equality of rise and fall times at the signal output;

• In output stages transistors with

channel width of 1 μm (NMOS) and 2.4 μm (PMOS) were used.

Simul mulation ation result ults

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Logic component Lapis Semiconductor SOI 0.2 µm AMS 0.35 µm Rise time [ps] Fall time [ps] Delay [ps] Area [µm2] Rise time [ps] Fall time [ps] Delay [ps] Area [µm2] Inverter 124 104 50 14.75 195 77 73 39.76 Not AND 257 194 114 22.12 282 120 106 55.86 Not OR 264 199 119 22.12 339 201 166 55.86 Exclusive OR 255 220 219 51.61 400 178 411 204.82 Exclusive NOR 293 246 150 51.61 506 229 252 111.72 D-type flip flop 138 140 386 125.34 235 140 829 279.30

− Results presented in table are based on simulations of schematics. − Cells with similar output current were selected from both libraries. − Designed elements have steeper output signal slope in most cases. − Five elements of the new library from among six that have been investigated have smaller delay time when compared to the elements of the AMS library. − Designed digital library achieved comparable speed with just 37% - 46% of area

• f similar item from the AMS library.

Ring ng oscill llators ators test struc ucture ures

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Each ring oscillator contains large number of gates arranged in series to accurately estimate the delay introduced by a single component based on oscillation’s period. Fourteen ring oscillators were designed:

• Ring_Inv0, Ring_Inv0_load1, Ring_Inv0_load2;
• Ring_Inv8, Ring_Inv8_load1, Ring_Inv8_load2;
• Ring_Inv0x150;
• Ring_Inv4;
• Ring_Nand20 and Ring_Nand20u;
• Ring_Nor20 and Ring_Nor20u;
• Ring_Xor20 and Ring_Xor20u.

Using the same masks set, the test structures were fabricated on Czochralski n-type (CZN), Floating Zone n-type (FZN) and Floating Zone p-type (FZP) substrates. Additionally, for FZN substrate results from two batches will be presented.

Measure urements ments and result ults

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Circuit name Simulated delay [ps] Measured delay Average [ps] RMS

• Av. / Sim [%]

Ring_NAND20 132,47 297,12 14,08 224 Ring_NAND20u 151,11 302,58 14,88 200 Ring_NOR20u 187,04 315,81 15,98 169 Ring_NOR20 254,94 369,19 18,54 145 Ring_XOR20u 323,58 565,51 26,81 175 Ring_XOR20 363,21 654,32 28,17 180 Ring_Inv4 104,26 146,63 6,44 141 Ring_Inv8 106,93 155,50 6,63 145 Ring_Inv8_load1 111,49 166,22 7,06 149 Ring_Inv8_load2 116,44 175,80 7,47 151 Ring_Inv0x150 108,48 226,32 11,43 209 Ring_Inv0 109,01 229,59 12,29 211 Ring_Inv0_load1 184,95 377,17 20,52 204 Ring_Inv0_load2 262,08 521,35 26,39 199

Averaged delay introduced by component calculated from all 12 chips disregarding wafer type.

Measure urements ments and result ults

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Averaged delay introduced by component but taking into account the difference in a wafer type (average delay measured in three chips of the same batch).

Circuit name Simulated delay [ps] 1J-HR1 (CZN) E2J-FZN 2JB-FZN 3JB-FZP Average [ps] RMS Average [ps] RMS Average [ps] RMS Average [ps] RMS Ring_NAND20 132,47 304,73 5,726 315,64 0,455 286,01 2,420 282,10 2,008 Ring_NAND20u 151,11 309,88 5,183 322,80 0,857 290,08 2,241 287,57 3,091 Ring_NOR20u 187,04 323,54 5,432 337,41 1,239 303,50 2,752 298,81 4,012 Ring_NOR20 254,94 379,55 6,235 393,50 1,177 354,36 1,905 349,34 4,433 Ring_XOR20u 323,58 578,72 10,136 602,02 0,994 541,98 3,925 539,34 3,278 Ring_XOR20 363,21 669,01 9,068 692,43 0,809 629,30 3,091 626,54 3,967 Ring_Inv4 104,26 149,97 1,539 155,41 0,585 140,50 0,741 140,63 0,729 Ring_Inv8 106,93 158,58 1,774 164,75 0,291 149,80 0,485 148,84 0,688 Ring_Inv8_load1 111,49 169,50 2,040 176,07 0,260 160,13 0,327 159,17 0,768 Ring_Inv8_load2 116,44 179,34 2,188 186,17 0,247 169,21 0,566 168,48 0,849 Ring_Inv0x150 108,48 233,58 3,679 240,51 1,186 217,90 2,880 213,31 2,344 Ring_Inv0 109,01 236,73 4,484 245,08 0,526 221,22 2,829 215,31 3,308 Ring_Inv0_load1 184,95 389,83 8,173 402,44 0,568 363,10 4,110 353,30 5,785 Ring_Inv0_load2 262,08 537,36 9,875 553,96 2,435 504,19 5,701 489,90 6,751

Digital al libra rary, ry, summary mary

• A digital library dedicated to currently developed FD-SOI 0.2 µm technology provided

by Lapis Semiconductor was designed.

• During the layout process a large emphasis on obtaining the lowest possible size of

layout cells was placed.

• Designed digital library allows automatic implementation of complicated digital block

using its descriptions in HDL.

• It was possible to achieve satisfactory timing with more than twofold decrease in
• ccupied area when compared to library created in AMS 0.35 µm technology.
• Test structures of some of the library components were fabricated and measured.
• Obtained results show typical discrepancy between simulations of schematic and

fabricated circuit performance.

• Test structures were produced on different substrates and no clear dependence was
• bserved.
• S. Głąb, M. Baszczyk, P. Dorosz, M. Idzik, W. Kucewicz, M. Sapor, P. Kapusta, Y. Arai, T. Miyoshi, A. Takeda, Synthetizable Digital Library

Created to Facilitate Design of SOI Detectors in 200 nm SOI Technology, ICSES 2014; proceedings of the International Conference on Signals and Electronics; http://ieeexplore.ieee.org/xpl/articleDetails.jsp?reload=true&arnumber=6948729

Thank you for your attention

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