SPARCInstructionSet CS217 Fall2001 1 LoadInstructions - - PDF document

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Fall2001 1

SPARCInstructionSet

CS217

Fall2001 2

LoadInstructions

• Movedatafrommemorytoaregister

ld{a}[address],reg

• Details

fetchedbyte/halfwordisright-justified leftmostbitsarezero-filledorsign-extended double-wordloadedintoregisterpair;mostsignificant wordinreg (mustbeeven);leastsignificantinreg+1 addressmustbeappropriatelyaligned u s b h d

Fall2001 3

StoreInstructions

• Movedatafromaregistertomemory

st{a}reg,[address]

• Details

rightmostbitsofbyte/halfwordarestored leftmostbitsofbyte/halfwordareignored reg mustbeevenwhenstoringdoublewords b h d

2

Fall2001 4

ArithmeticInstructions

Generalform

add{x}{cc}src1,rc2, reg sub{x}{cc}src1,src2,reg

Details

src1 andreg mustberegisters src2 maybearegisterorasigned13-bitimmediate add%o1,%o2,%g3 sub%i1,2,%g3

Librariesoftenprovidemultiplyanddivide

.mul .div.rem...

Fall2001 5

DataMovement

• Loadaconstantintoaregister

setvalue,reg

implementedas

sethi%hi(value),reg

• rreg,%lo(value),reg

if%hi(value)==0,omit sethi if%lo(value)==0,omit or

reg 4 %hi(value)

31 29 24 21

Fall2001 6

DataMovement(cont)

• Example:directaddressing

seta,%g1sethi%hi(a),%g1 ld[%g1],%g2or%lo(a),%g1 ld[%g1],%g2

fasteralternative

sethi%hi(a),%g1 ld[%g1+%lo(a)],%g2

3

Fall2001 7

DataMovement(cont)

• Clearingregistersandmemory

add%g0,%g0,%o1 st %g0,[%i1] stb %g0,[%i1]

Fall2001 8

SyntheticInstructions

• Implementedbyassemblerwithoneor

more“real”instructions;alsocalledpseudo- instructions

Real

• r%g0,src,dst

add%g0,%g0,reg st %g0,[addr] sub%g0,dst,dst sub%g0,src,dst adddst,1,dst subdst,1,dst Synthetic movsrc,dst clrreg clr [addr] neg dst negsrc,dst incdst decdst

Fall2001 9

BitwiseLogicalInstructions

Assembly

and{cc}src1,src2,dst andn{cc}src1,src2,dst

• r{cc}src1,src2,dst
• rn{cc}src1,src2,dst

xor{cc}src1,src2,dst xnor{cc}src1,src2,dst

CorrespondingC

dst = src1& src2 dst = src1& ~src2 dst = src1| src2 dst = src1|~src2 dst = src1^ src2 dst = src1^~src2

4

Fall2001 10

BitwiseLogical(cont)

• Complement

negreg notreg

• SyntheticInstructions

btst bits,reg bset bits,reg bclr bits,reg btog bits,reg

• Example

btst 0x8,%g1 sub%g0,reg,reg (2’scomp) xnorreg,%g0,reg (1’scomp) andccreg,bits,%g0

• rreg,bits,reg

andnreg,bits,reg xorreg,bits,reg

Fall2001 11

ShiftInstructions

• Generalform

s src,,reg(note:nosla)

• sll and srl fillwith0; sra fillswithsignbit
• For2’scomplementnumbers

srareg,n,reg divides reg by2 sllreg,n,reg multiplies reg by2 shiftinstructionsdonotmodifytheconditioncodes l r l a reg1

0..31

n n

Fall2001 12

FloatingPointInstructions

• Performedbyfloatingpointunit(FPU)
• Use32floatingpointregisters:%f0…%f31
• Loadandstoreinstructions

ld[address],freg ldd [address],freg stfreg,[address] stdfreg,[address]

• OtherinstructionsareFPU-specific

fmovs,fsqrt,fadd,fsub,fmul,fdiv,…