Steady-State Scheduling on Heterogeneous Platforms Matthieu Gallet - - PowerPoint PPT Presentation
tel-00637362, version 1 - 1 Nov 2011 Steady-State Scheduling on Heterogeneous Platforms Matthieu Gallet Advisors: Yves Robert and Fr ed eric Vivien Ecole Normale Sup erieure de Lyon GRAAL team, Laboratoire de lInformatique du
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◮ Presentation of the Divisible Load Theory ◮ Scheduling divisible loads on a processor chain
◮ Mono-allocation schedules of task graphs on heterogeneous
◮ Dynamic bag-of-tasks applications ◮ Computing the throughput of replicated workflows ◮ Task graph scheduling on the Cell processor 3/64
◮ Presentation of the Divisible Load Theory ◮ Scheduling divisible loads on a processor chain
◮ Mono-allocation schedules of task graphs on heterogeneous
◮ Dynamic bag-of-tasks applications ◮ Computing the throughput of replicated workflows ◮ Task graph scheduling on the Cell processor 3/64
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◮ undefined for a continuous flow of data sets ◮ does not benefit from regular problem structure 7/64
◮ undefined for a continuous flow of data sets ◮ does not benefit from regular problem structure
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P2 P1 P3 P4 P5 P6 P7 T2 F3,4 F2,3 F1,2 T4 T3 T1 10/64
P5 P3 P3 P1
T2 F3,4 T1 T4 F1,2 F2,3 T3 11/64
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T1 T4 T3 F2,3 T2 F1,2 F3,4 12/64
T1 T4 T3 F2,3 T2 F1,2 F3,4 12/64
P7 P2 P6 P5 P4 P7 P1
T3 F2,3 F3,4 T1 T4 F1,2 T2 12/64
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P4 P1 P6 P2 P7 P5 P3
F3,4 T1 T2 T3 T4 F2,3 F1,2 13/64
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F3,4 T1 T2 T3 T4 F2,3 F1,2 13/64
P1 P6 P2 P7 P5 P3 P4
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T4 T2 F1,2 F2,3 F3,4 T3 T1 13/64
P7 P5 P3 P4 P1 P6 P2
T4 T2 F1,2 F2,3 F3,4 T3 T1 13/64
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T1 F3,4 F2,3 F1,2 T2 T3 T4 13/64
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◮ Strict One-Port: a processor can either compute or perform a
◮ Full-Duplex One-Port: a processor can either compute or
◮ One-Port with overlap of computation by communications
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◮ Limited incoming bandwidth bwin
q
◮ Limited outgoing bandwidth bwout
q
◮ Limited bandwidth per link bwq,r
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◮ assign “largest” task to best processor ◮ continue with second “largest” task, assign it to the processor
◮ . . .
◮ take communication times into account when sorting tasks ◮ when mapping a task, select the processor such that the
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◮ Select the αk
i with maximum value
◮ Set αk
i to 1
◮ Select a task Tk not yet mapped ◮ Randomly choose a processor Pi with probability αk
i
◮ Set αk
i to 1
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◮ for all tasks, we test all possible immediate neighborhoods, and
◮ for a given mapping, we sort all resource occupation times by
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◮ Evaluate the mapping of Tk and its neighbors on each
◮ Definitely assign Tk to best processor
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◮ “Small problems”: 8–12 tasks ◮ “Large problems”: up to 47 tasks (MLP not used) ◮ for each application, we compute a CCR = communications
◮ we try to cover a large CCR range 30/64
Optimal Large communications Small communications 0.01 Normalized throughput log(CCR) 2.5 2 1.5 1 0.5 10 4 2 1 0.4 0.2 0.1 0.04 0.02 Upper bound Delegate
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0.04 0.02 Large communications Small communications Optimal Normalized throughput 1.2 1 0.8 0.6 0.4 0.2 log(CCR) 10 4 2 1 0.4 0.2 0.1 0.01 Delegate HEFT Data-parallel
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Optimal 0.01 0.02 0.04 0.1 0.2 0.4 1 2 4 10 log(CCR) 0.2 0.4 0.6 0.8 1 1.2 Normalized throughput Small communications Large communications Refined Greedy Simple Greedy Delegate Clustering
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0.01 0.02 0.04 0.1 0.2 0.4 1 2 4 10 0.2 0.4 0.6 0.8 1
Optimal Large communications log(CCR) Small communications Normalized throughput
RLP RAND RLP MAX Neighborhood Delegate
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EIB P0 PPE0 SPE4 SPE3 SPE0 SPE1 SPE7 SPE6
MEMORY
SPE2 SPE5 P3 P7 P8 P2 P1 P4 P5 P6
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EIB P4 P5 P1 P2 P8 P7 P3 SPE5 PPE0 SPE4 SPE3 SPE0 SPE6
MEMORY
SPE2 SPE1 SPE7 P6 P0
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P6 SPE2 SPE6 SPE7 SPE1 SPE0 SPE3 SPE4 PPE0 SPE5 P3 P7 P8 P2 P1 P4 P5 P0
MEMORY
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EIB PPE0 SPE4 SPE3 SPE0 SPE1 SPE7 P6 P0 P4 P5 P1 SPE6
MEMORY
P2 SPE2 P8 P7 P3 SPE5
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EIB P0 PPE0 SPE4 SPE3 SPE0 SPE1 SPE7 SPE6
MEMORY
SPE2 SPE5 P3 P7 P8 P2 P1 P4 P5 P6
◮ at most 16 simultaneous incoming communications for each SPE ◮ at most 8 simultaneous communications
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◮ readk: data to read before executing Tk ◮ writek: data to write after the execution of Tk ◮ peekk: number of next data sets to receive before executing Tk
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P2 P3 P6 P5 P4 P7
P1
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P2
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P7 P4 P6
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P7 P4 P6
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P2 P4 P7 P5 P6 P3
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Comments on “Design and performance evaluation of load distribution strategies for multiple loads
Matthieu Gallet, Yves Robert, Fr´ ed´ eric Vivien, Journal of Parallel and Distributed Computing, 68(2), 2008 Divisible Load Scheduling Matthieu Gallet, Yves Robert, Fr´ ed´ eric Vivien, Introduction to Scheduling , 2009
Scheduling communication requests traversing a switch: complexity and algorithms Matthieu Gallet, Yves Robert, Fr´ ed´ eric Vivien, Proceedings of the 15th Euromicro Workshop on Parallel, Distributed and Network-based Processing (PDP’2007) , 2007 Scheduling multiple divisible loads on a linear processor network Matthieu Gallet, Yves Robert, Fr´ ed´ eric Vivien, Proceedings of the 13rd IEEE International Conference on Parallel and Distributed Systems (ICPADS’07) , 2007 Efficient Scheduling of Task Graph Collections on Heterogeneous Resources Matthieu Gallet, Loris Marchal, Fr´ ed´ eric Vivien, Proceedings of the 23rd International Parallel and Distributed Processing Symposium (IPDPS’09) , 2009 Allocating Series of Workflows on Computing Grids Matthieu Gallet, Loris Marchal, Fr´ ed´ eric Vivien, Proceedings of the 14th IEEE International Conference on Parallel and Distributed Systems (ICPADS’08) , 2008 Computing the throughput of replicated workflows on heterogeneous platforms Anne Benoit, Matthieu Gallet, Bruno Gaujal, Yves Robert, Proceedings of the 38th International Conference on Parallel Processing (ICPP’09) , 2009 62/64
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