Survey of Domain- Specific Languages for FPGA Computing Nachiket - - PowerPoint PPT Presentation

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Survey of Domain- Specific Languages for FPGA Computing Nachiket - - PowerPoint PPT Presentation

Mar 24, 2023 435 likes •932 views

Survey of Domain- Specific Languages for FPGA Computing Nachiket Kapre nachiket@ieee.org Some goodness metric Expressiveness (Freedom) 2 Some goodness metric Trumps attack on judge Expressiveness (Freedom) 3 Singapores contempt

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Survey of Domain- Specific Languages for FPGA Computing

Nachiket Kapre nachiket@ieee.org

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Expressiveness (Freedom) Some goodness metric

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Expressiveness (Freedom) Some goodness metric Trump’s attack on judge

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Expressiveness (Freedom) Some goodness metric Singapore’s contempt of court bill Trump’s attack on judge

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Expressiveness (Freedom) Some goodness metric Singapore’s contempt of court bill Trump’s attack on judge

Singapore: Contempt of court bill is a threat to freedom of expression

Donald Trump's hate-filled rhetoric & bigoted scapegoating flies in the face of equality & MUST be rejected. https://twitter.com/amnesty/status/674053786520915969

https://www.amnesty.org/en/latest/news/2016/08/singapore-contempt-of-court-law/

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Expressiveness (Freedom) Some goodness metric Classic HDLs

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Expressiveness (Freedom) Some goodness metric Classic HDLs DSLs

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Outline

  • Review of FPGA Design Flow


— Where we stand?
 — Need for DSLs

  • Classification of DSLs
  • Code Vignettes
  • Experimental Results

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Outline

  • Review of FPGA Design Flow


— Where we stand?
 — Need for DSLs

  • Classification of DSLs
  • Code Vignettes
  • Experimental Results

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FPGA flow

  • FPGA flow longer, more

complex

  • Problem 1: Write low-level

Verilog code

  • Problem 2: Wait hours to

compile
 (adds insult to injury)

  • Problem 3: Long verification

feedback cycles.

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Example code sketches

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Example code sketches

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What’s different?

  • What makes the C

code smaller?

  • Clocking/Reset?
  • Explicit pipelining
  • Type information


— registers, wires, number of bits

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Simple forms of parallelism

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Simple forms of parallelism

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Limits of OpenCL/HLS

  • One alternative to HDLs — OpenCL/HLS flow
  • Restricted subset of C (no pointers, no complex data

sharing) —> sacrifice freedom for speed

  • Drawbacks:


— Overheads due to implicit assumptions
 — more area, slower design, not fully optimised
 — Only really addresses time-to-compilation
 — still need to do synth + P&R

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Outline

  • Review of FPGA Design Flow


— Where we stand?
 — Need for DSLs

  • Classification of DSLs
  • Code Vignettes
  • Experimental Results

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Domain-Specific Languages

  • “Beauty lies in the eye of the beholder”
  • Conventional “application-domain” view


— finance, HPC, radio, multimedia, networking, databases, security.

  • Suggest two alternate views in this paper…

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Axes of classification

  • (1) Conventional “application-domain” view


— focus on end-user of FPGA technology

  • (2) “compute-model” view


— analogous to Berkeley’s Ptolemy classification

  • (3) “design” view


— behind-the-scenes tinkerers, library developers, system builders, academics

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Axes of classification

  • (1) Conventional “application-domain” view


— focus on end-user of FPGA technology

  • (2) “compute-model” view


— analogous to Berkeley’s Ptolemy classification

  • (3) “design” view


— behind-the-scenes tinkerers, library developers, system builders, academics

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P4

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P4

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P4 Lua/Torch

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Outline

  • Review of FPGA Design Flow


— Where we stand?
 — Need for DSLs

  • Classification of DSLs
  • Code Vignettes
  • Experimental Results

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Matlab HDL Coder

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Maxeler

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SCORE

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MSR Accelerator C#

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JHDL

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CHISEL

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Outline

  • Review of FPGA Design Flow


— Where we stand?
 — Need for DSLs

  • Classification of DSLs
  • Code Vignettes
  • Experimental Results

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Experimental Evaluation

  • NTU MSc Embedded Systems cohort


— Class of 2014-15
 — ~25-30 students

  • 3-4 students per DSL
  • One 4hr lab session devoted to working on the

ax2+bx+c mapping example

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Compiler modified

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Vendor HLS

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Limited to arith expr

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Tool config tough

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Dated EDIFs

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Hardware students disliked

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Conclusions

  • Summary


— Vast space of DSLs
 — Various states of rot — unmaintained projects

  • How to navigate?


— First attempt: Does HLS/OpenCL work for you
 — Next try: Well-supported tools such as Matlab HDLCoder, Tabview FPGA, Maxeler Dataflow
 — Finally: Check amongst the DSLs, or write your own

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