Synchronous logical networks I Digital Systems M 1 Asynchronous - - PowerPoint PPT Presentation

Synchronous logical networks I

Digital Systems M

1

Asynchronous network problems

• The behaviour depends on the feedback delays with all related

possible malfunctionings (different delays)

2

• The behaviour depends on the input hazards (which in any case can’t

be exactly concurrent) and prevents the detection of repeated input sequences (i.e. the sequence 00-00-11-01 is the same as 00-11-01) SOLUTION

• An

«artificial» input concurrency detection and forced and controlled feedback delays

Synchronism signal

• If the pulse is short enough and less than the combinatorial network delay (that is the

combinatorial network minimum delay) the new s/r0..k produced by the combinatorial network do not reach the blocking AND before the AND outputs are zeroed making the SR FF stable (the SR FF with both inputs zero doesn’t change status). Only during the following τ pulse the new FF outputs values are transmitted to the combinatorial network with no feedabck effets again. Forced feedback alignment.

Combinatorial network

X0..n

Z0..m s/r0..k Y0..k

τ

FF SR0..k

Synchronism signal

3

• It must be noticed that this way the combinatorial networks inputs too are forcibly «aligned»

as far as the status is concerned. No «race» problems (but for the output in the Mealy case)

• The outputs are almost perfectly aligned (that is they are synchronous) if the sequential

machine is Moore type (the outputs depend only from the state variables) and the FFs switch concurrently (which is very likely)

Synchronism signal

• The synchronism signal is always referred to as clock

4

Clock T

• Normally the clock signal is a regular repetitive square (or rectangular) wave of T period

(but not necessarily)

• A SR FF with a clock signal is referred to as synchronous SR (which in the real systems is

never used)

• What problems arise with the clock signal of the figure ? The pulse duration should be

extremely narrow since a combinatorial network can consist even of a single wire and in this case the delay is only the wire propagation delay! In practice it cannot be implemented

The synchronous FFs

• There are several synchronous FFs but nowadays only the DFF is used whose

behaviour was previously analysed as an asynchronous network but which here is used as a synchronous FF (in its 74xx74 version) D Q !Q CK D

• The DFF has this name name because D stands for Delay. In fact the output Q follows the

input D with a T period delay (if the input signal is synchronous – that is is generated concurrently with the clock – respecting however setup and hold times – for instance by a network controlled by other DFFs using the same clock)

• r in presence of the first

clock rising edge. D Q !Q CK D PR CL The signals !CL(ear) and !PR(eset) act asynchronously that is immediately, independently from the clock

5

• The triangle on the clock input (CK) indicates that the FF is edge triggered that is it

switches on the positive edge of the clock

6

The DFF switches ONLY during the transition of CK fro 0 o 1. This corresponds to the very short pulse τ seen before. If the transition is fast enough the combinatorial network cannot react before the CK transition is finished

Combinatorial network

X0..n

Z0..m y0..k Y0..k

Clock

D0..k Q0..k

FFD0..k

CK D0..k Q0..k

CK

The clock of the DFF must switch from 0 to 1 only when the combinatorial network is stable (quiet). The transfer of the DFF input to its outputs (transition time) must fast enough to grant the the new D inputs generated by the combinatorial network because of the new values of Yi arrive after the end of the CK transition. Then there is a solid time period for the combinatorial network to reach a new stable state. The period of the CK must be in any case greater than the time required by the combinatorial network to reach its stable state.

Let’s consider the DFF

DFF D CK Q Q* D CK Q QN

CK D Q

7

entity DFF_1 is Port ( D : in std_logic ; CK : in std_logic ; Q : out std_logic; QN : out std_logic ); end DFF_1; architecture Behavioral of DFF_1 is begin process_FF: process(CK,D) begin if (CK'event) and (CK='1') then Q <= D; QN <= not(D); -- Careful! QN <= not(Q) must not be used !!!!!!

• - otherwise QN switch would not be concurrent with Q

end if; end process process_FF; end Behavioral; “if (CK'event) and (CK='1')” means that the switch occurs in presence of an edge of CK and the final value is 1 (CK=1). Rising edge !

8

• Asynchronous commands A_SET and A_RES have precedence over the other inputs

DFF D CK Q Q* D CK Q QN A_SET A_RES A_SET A_RES

DFF with Set and Reset (VHDL)

9

• The two signals must not be activated concurrently (nonsense)
• In our case we want to model the DFF so as A_RES has precedence over A_SET

entity DFF_asynchronous_commands is Port ( CK : in std_logic; D : in std_logic; A_SET : in std_logic; A_RES : in std_logic; Q : out std_logic; QN : out std_logic); end DFF_asynchronous_commands; architecture Behavioral of DFF_asynchronous_commands is begin Process_FF: process(CK, A_SET, A_RES, D) begin

• - positive logice

if (A_RES='1') then Q <='0'; QN <='1'; elsif (A_SET = '1') then

• - only if A_RES inactive

Q <='1'; QN <='0'; elsif (CK='1') and (CK'event) then Q <= D; QN <= not(D); end if; end process process_FF; end Behavioral; 10

Asynchronous Reset (A_RES=1, A_SET=0) Both asynchronous commands active (A_RES=1, A_SET=1): asynchronous reset has higher priority (see VHDL) Asynchronous Set (A_RES=0, A_SET=1) Positive logic !

11

12

In Vivado the DFF (as other basic components can be found as ready_to_use elements. In tools=>language templates it is possible to find it. Each template depends on the type

• f the used device (artix in this example)

13

• FDCE : In order to incorporate this function into the design,
• VHDL : the following instance declaration needs to be placed
• instance : in the architecture body of the design code. The
• - declaration : instance name (FDCE_inst) and/or the port declarations
• code : after the "=>" assignment maybe changed to properly
• : connect this function to the design. All inputs must be
• : connected.
• Library : In addition to adding the instance declaration, a use
• - declaration : statement for the UNISIM.vcomponents library needs to be
• for : added before the entity declaration. This library
• Xilinx : contains the component declarations for all Xilinx
• primitives : primitives and points to the models that will be used
• : for simulation.

library IEEE; use IEEE.STD_LOGIC_1164.ALL;

VHDL source

14

• - NB If you want to use the VHDL functions as FDCE you must use UNISIM

library UNISIM; use UNISIM.VComponents.all; entity Source is Port ( Q: out std_logic; C: in std_logic; CE: in std_logic; CLR: in std_logic; D: in std_logic ); end Source;

• - FDCE: Single Data Rate D Flip-Flop with Asynchronous Clear and
• Clock Enable (posedge clk).
• Artix-7
• - Xilinx HDL Language Template, version 2016.4

architecture Behavioral of Source is begin FDCE_inst : FDCE generic map ( INIT => '0') -- Initial value of register ('0' or '1') port map ( Q => Q, -- Data output C => C, -- Clock input CE => CE, -- Clock enable input CLR => CLR, -- Asynchronous clear input D => D -- Data input ); end behavioral;

15 library IEEE; use IEEE.STD_LOGIC_1164.ALL;

• - Uncomment the following library declaration if using
• - arithmetic functions with Signed or Unsigned values
• -use IEEE.NUMERIC_STD.ALL;
• - Uncomment the following library declaration if

instantiating

• - any Xilinx leaf cells in this code

library UNISIM; use UNISIM.VComponents.all; entity Test is end Test; architecture Behavioral of Test is component source Port ( Q: out std_logic; C: in std_logic; CE: in std_logic; CLR: in std_logic; D: in std_logic ); end component; signal Q: std_logic := '0'; signal C: std_logic := '0'; signal CE: std_logic := '0'; signal CLR: std_logic := '0'; signal D: std_logic := '0';

VHDL test

16 begin uut: Source PORT MAP ( D => D, C => C, Q => Q, CE => CE, CLR => CLR ); stim_proc: process begin wait for 20 ns; D <= '1'; CE <= '1'; wait for 20 ns; C <= '1'; wait; end process; end Behavioral;

17

VHDL behavioural simulation

Synchronous sequential networks

• The synthesis is performed as in the case of an asynchronous network with direct feedback but

inputs remaining constant are considered by the network as different since they are considered in different periods and therefore in presence of possible different states of the FFs

See the architecture of the asynchronous networks with SR FF feedback where S=!R 18

Combinatorial network

X0..n

Z0..m y0..k Y0..k

Clock

D0..k Q0..k

FFD0..k

CK D0..k Q0..k

CK

• What matters in this case is

the clock positive edge: the time distance between two consecutive rising edges (respecting setup e hold times) DOESN’T count

• Clock period (frequency) must be greater (smaller) than the max combinatorial network delay.

The combinatorial network must be stable after a clock positive edge before a new clock positive edge can occur

• The clock rising edge differentiates input and output (it separates them from the time point of

view)

Synchronous Sequential Networks (SSN)

k feedback DFFs All with the same clock of T period In this case: Moore or Mealy ?

S O S* I

t t+T t+2·T t-T

CK

k (k) DFF

S S*

CK

RC

I O

19

The DFF as fundamental SSN element

If a periodic signal is sent to CK (clock) input, the DFF (D = Delay) delays the output signal Q a time equal to the period T if the change of D is logically (but not physically) concurrent with CK (but always respecting setup and hold times) Qn+1 = Dn

D CK Q

T T T T

NB: The concept of concurrency could seem to be in contrast with the need of respecting setup and hold times. As a matter of fact the inputs of a synchronous network are in the great majority of cases the outputs of other networks which have the same clock and therefore with their delays which grant automatically the respect of setup and hold. Therefore the variations of the inputs are always a little later than the clock edge. See later the behaviour of the shift registers

DFF

D CK Q Q*

D CK Q Q*

NB:since here the time is discrete, n and n+1 (periods) are used instead of T e T+τ

20

Synchronous Sequential Networks

• The states changes occur only with the rising edges of the clock and therefore with T period (if

the clock is periodical)

21

• The network changes its state every T and therefore if a very responsive network is required, as

far as the outputs are concerned, the Mealy model must be adopted

• The states evolution is independent from the combinatiorial network delays (provided the distance

between the rising edges of the clock is greater that the maximum delay of the combinatorial network)! Therefore no critical races problem

• Within the same system (i.e. a processor) more SSNs can exist present, not necessarily with the

same clock

• SSNs can be more easily designed than the ASNs

Clock gating and clock glitch

In the synchronous sequential networks unwanted clock glitches mus be avoided which could induce unwanted DFF switches.

CK P CK_G

Clock glitches → possible unwanted DFF switch

X CK Q Q* FFD

D CK Q Q*

CK_G

Decoding network

I[n-1..0] P

t

NO !!

Obviously it depends on the spurious glich duration: if too narrow the FF could be not triggered (the clock pulse must always have a minimum width which depends on the FF technology: when too narrow either is not sensed by the FF or can cause metastability). The clock gating is not prohibited but is a risk to be avoided when possible.

22

For instance because of the different delays of the n signals I[n-1..0] of a decoding network, hazards (glitches) can occur provoking the “clock gating“ effect

For transitions which must or must not take place depending on a decoding network the solution of the figure must be adopted. If the decoding output is 1 Qn+1 = Dn otherwise Qn+1 = Qn

X CK Q Q* FFD

D CK Q Q*

I[n-1..0] P

t

1

SEL

1

SEL

Decoding network

23

Clock gating and clock glitch

The clock gating, in addition to cause potential glitches produces also a “clock-skew” (misalignment). Let’s consider two SSN, DFF1 and DFF2

Clock gating e clock-skew

CK CK_G

τAND τAND

The two networks clocks are out of phase beacuse of the inserted AND delay time τAND. This phenomenon - clock-skew - is potentially very dangerous since DFF-2 could sample the new (and not the previous) value of DFF-1 albeit the clock should be the same NB: The “clock-skew” is not only caused by the clock gating but also (for example) by different electrical paths

I1 CK B B* CK_G P I2 CK A A*

τAND

DFF-1

D CK Q Q*

DFF-2

D CK Q Q*

24

Input synchronization

• Up to now we have implicitly assumed that the inputs of a synchronous network switch

synchronously with the clock

X0..n

Combinatorial network Z0..m y0..k Y0..k

Clock

D0..k Q0..k

DFF0..k

CK D0..k Q0..k

CK

Combinatorial network

• As a matter of fact, the real situation is normally different. Let’s consider for instance a push

button as the input of a synchronous network. Its status change can occur any time.

25

• This is true if the inputs come from a Moore type network where the outputs depend only

from the state, which switches synchronously with the clock.

• In the network of the figure (Moore) the outputs are in any case synchronous with the clock: if

the input X0..n change asynchronously from the clock their changes are detected by the network feedback FFs only at the clock positive edge and therefore the network behaviour is the same it would occur if the inputs were synchronous

Input synchronisation

• The situation is different however with a Mealy network

Combinatorial network

X0..n

Z0..m y0..k Y0..k

Clock

D0..k Q0..k

FFD0..k

CK D0..k Q0..k

CK

• In this case an asynchronous input change triggers, in general, an asynchronous
• utput change

26

27

10 00 01 01 01 11 00 01 10 00 01 11 G,0 F,0 E,1 B,0 A,0 10 00 C,0 01 10 00 10 00 10 10 D,0 11 11 11 10 11

Synchronous Safe

Example: the safe (with a two keys keyboard) opens only if the inputs temporal sequence is 00-01-01-10. Each sequence violation restarts the system. NB Since the inputs are sampled the sequence 01-01 is possible and meaningful

For each state ALL input configurations !! Not always so (i.e. mechanical or electrical constraints)!!

The states are not necessarily stable for the input configurations which led to them

NB: It can be assumed that the inputs change concurrently with the state variables but this is not necessary. If the network is Moore type even if the inputs change in the middle of a clock period the behaviour from the state point

• f view (and therefore from the outputs point of view) is in any case the same

(each input variation is sampled

• nly at the period end))

11

B

00 01 11 10

F A G

A

B C A G

B

B D A G

C

B F A E

D

B F A G

E

B F AA- G

F

B F A G

G 1

X1X2

Synchronous Safe

NB: in this esample there are not don’t cares for the states. Instead of compatibile states therefore there are equivalentd (disjoint) states. In general when two states for the same inputs have the same outputs and lead to the same states or equivalent states they are called indistinguishable. Obviously the system description could include some impossible inputs configurations: in this case we go back to the compatibility concept. The same applies when one ore more outputs are don’t care (a very unlikley situation since all states last one period)

28

10 00 01 01 01 11 00 01 10 00 01 11 G,0 F,0 E,1 B,0 A,0 10 00 C,0 01 10 00 10 00 10 10 D,0 11 11 11 10 11

Synchronous Safe

Equivalence (not compatibility) classes [AFG] => α [B] => β [C] => γ [D] => δ [E] => ε

B

00 01 11 10

F A G

A

B C A G

B

B D A G

C

B F A E

D

B F A G

E

B F AA- G

F

B F A G

G 1

X1X2

B C D E F G A B C D E F

CF FD CD CF GE CF GE DF GE

• CF

DF GE

• C F

DF GE

• β

00 01 11 10

α α α

α

β γ α α

β

β δ α α

γ

β α α ε

δ

β α α α

ε

X1X2

1

NB: In case of fully specified tables the maximal equivalence classes have NO states in common (the transitive property is valid). Since they are disjoint, all of them must be used and therefore there is NO closure problem Obviously 5 states: 4 belongs to the correct sequence and one is

• ut of it

29

β

00 01 11 10

α α α

α

β γ α α

β

β δ α α

γ

β α α ε

δ

β α α α

ε

X1X2

1

Synchronous Safe

001

00 01 11 10

000 000 000

000

001 011 000 000

001

001 010 000 000

011

001 000 000 100

010

001 000 000 000

100 X1X2

−− −− −− −−

101

−− −− −− −−

111

−− −− −− −−

110 1

• Y1Y2 Y3

α => 000 β => 001 γ => 011 δ => 010 ε => 100 D1= X1!X2Y2!Y3 D2=!X1X2Y3 D3=!X1!X2+!X1!Y2Y3 Z =Y1

Using DFFs the D inputs synthesis is achieved by synthesizing Yi (Yn+1=Dn) No race problems: free states coding

30 NB: The synthesis is made on the assumption that the opening input configurations follow synchronously with a distance of a period. Should the safe open ONLY when the sequence is correct no matter how many times a single correct input is repeated an auto-ring must be provided in the corresponding state

31

Behavioural Simulation

32

Post-route Simulation

If Mealy ?

B

00 01 11 10

F A G

A

B C A G

B

B D A G

C

B F A E

D

B F A G

E

B F AA- G

F

B F A G

G 1

X1X2

B,0

00 01 11 10

F,0 A,0 G,0

A

B,0 C,0 A,0 G,0

B

B,0 D,0 A,0 G,0

C

B,0 F,0 A,0 E,1

D

B,0 F,0 A,0 G,0

E

B,0 F,0 A,0A-G,0

F

B,0 F,0 A,0 G,0

G

X1X2

Synthesize and simulate with Xilinx

33

In this case the safe opens as soon as the input becomes 10 in state D. Obviously this implementations opens the safe one period in advance compared with the Moore implementation

Monoimpulsor A

D1 Q1 !Q1 CK DFF D2 Q2 !Q2 CK DFF

Z D Clock

Here the asynchronous input D is synchronized by the DFFs.The output Z is synchronous with the clock

The aim is to generate a synchronous output pulse lasting one period when a «1» of an asynchronous input is detected. A further output pulse can be generated only when a «0» input is sampled and then a «1» is sampled again and so on

34

Clock D Z Q1 !Q2

Complement (time diagram starts after D=0 for several periods)

D1 Q1 !Q1 CK DFF D2 Q2 !Q2 CK DFF Z D Clock

Monoimpulsor A

1 1 A,0 B,1 C,0 1

A A A

• B

C C

• D

Q2 Q1

B 1 C

• Z

1

• A

00

• 00

00 10

• 11

11

D Q2 Q1

D 01 1 C 11 B 10 Z

• 1

A 00 00 10 11 01 B C D A

Q1=D Q2= Q1 Z=Q1!Q2

Moore necessarily if we want the output synchronous with the clock!

Q1=D Q2= DQ1 Z=Q1!Q2

A B C D 00 00 01 01 10 10 11 11

D Q2 Q1

01 1 11 10 Z 1 00

Same behaviour! 35 Synchronous network: no races!!

But using D … (A and D indistinguishable)

D1 Q1 !Q1 CK DFF D2 Q2 !Q2 CK DFF

Z D Clock Monoimpulsor B

A Mealy network: with an asynchronous input we have an asynchronous output

36

Clock D Z Q1 !Q2

Z lasts a period plus the inizial phase (D>period) Here Z duration depends on the input only (D<period)

(time diagram starts after D=0 for several periods)

D !Q Q CK DFF

Z D Clock Monoimpulsor C

Mealy network: with an asynchronous input we have an asynchronous output Z =1 if D=1 and is sampled

37

After the DFF has sampled a 1, if the input oscillates then the output

• scillates until the DFF samples a 0

Clock D Z Q

(time diagram start after D=0 for several periods)

Monoimpulsors A, B e C

• The exact state diagram corresponding to the real behaviour of

monoimpulsors B and C CANNOT be drawn because the two networks (Mealy type) are NOT synchronous. A synchronous state diagram implies that the inputs too are synchronous, which is not the case with B and C

38

• This is not the case of the monoimpulsor A either, since although the

input is asynchronous the output (Moore type) depends on the states

• nly. The network behaviour makes internally synchronous the inputs

which are physically asynchronous

• A real state diagram of monoimpulsors B and C can be designed only

using an asynchronous analysis, that is “opening” the DFF. Obviously it is always possible to design the two networks without the DFFs starting from an asynchronous traditional states diagram.

Q=1 Q=0

39

Monoimpulsor C (asynchronous description – both inputs cannot change at the same time): design a network with two inputs C and D and an output Z. The output Z is zero if D=0 independently from C. A transition of C from 0 to 1 samples always D and Z=1 if both the sampled value and D are 1

10,0 B 10,0 01,1 01,1 F 01,0 D 11,- 11,0 C 10,- 11,1 E 00,0 A CD,Z 11,0 10,0 11,1 00,0 01,0 00,0 11,1 00,0 G 00,0 01,1 10,0 H 10,0 00,0 01,0

A,0

00 01 11 10

D,0

• B,0

A

A,0

• C,0

B,0

B

• D,0

C,0 B,0

C

A,0 D,0 E,-

• D
• F,1

E,1 H,1

E

G,1 F,1 E,1

• F

G,1 F,1

• B,-

G

C D

G,1

• E,1

H,1

H

[ABC] [AD] [EFH] [FG] [ABC] [D] [EFH] [G] α β γ δ

α,0

00 01 11 10

β,0 α,0 α,0

α

α,0 β,0 γ,− −−

β

δ,1 γ,1 γ,1 γ,1

γ

δ,1 γ,1 −− α,−

δ

C D

B C D E F G A B C D E F

• CE
• H
• G
• CE

BH BH

41

α,0

00 01 11 10

β,0 α,0 α,0

α

α,0 β,0 γ,− −−

β

δ,1 γ,1 γ,− γ,1

γ

δ,1 γ,1 −− α,−

δ

C D

This is the state table of the DFF (see asynchronous networks) with a different output

Y1= y2C + y1!C Y2= y2C + D!C Z = y1D

00,0

00 01 11 10

01,0 00,0 00,0

C

00

00,0 01,0 11,− −−

01

10,0 11,1 11,1 11,0

11

10,0 11,1 −− 00,−

10

D y2 y1

α β γ δ

Post route simulation.

Input

42

Xilinx Monoimpulsors

Input: X ( respecting setup and hold times) Multiple outputs: ZA monoimpulsor 'A' ZB monoimpulsor 'B' ZC monoimpulsor 'C‘

Behavioural simulation Post-route simulation

43 Arrow => sampling delay

44

A retriggerable one-shot (trigger => activation signal) is a circuit which generates a Z output pulse lasting T (T presettable) after a positive edge of an input signal X. When another positive edge of X occurs during the pulse Z, the circuit extends the pulse Z of another T time. Design a synchronous retriggerable one-shot (Moore) which using an input signal X asynchronous to the clock (of frequency f=1/T) produces in a retriggerable way a pulse of 3 clock periods, synchronous with the clock.

3 Normal one-shot Retriggerable one-shot

1 X 1 1

G,1 F,1

1

A,0

1

D,1 C,1 B,1

1

E,0

The outputs becomes 1 with the first clock positive edge sampling X=1. From each state the number of branches is equal to the number of input configurations !!! 45

NB Synchronous output

With input=0 the three periods

• utput

is in any case produced, which is extended in case an input=1 is sampled again With X=1 at least a three periods output

1 X A A F C B A E D G D C 1 1 1 B A E G B F A B G 1 1 E B D C E F

A B C D E F

G

FG CD BE AF CE FG BC AG DE DB AG DB AG BE BE AG AF CB

All states are distinguishable

46

1 X A A F C B A E D G D C B A E G B F A B G 1 1 1 1 1 E

X Y2 Y1Y0

00 01 11 10 00 01 11 10

(D2D1D0)n

000 000 100 001 101 110 001 010 000

• 100

110 000 001 011

D2 = !X!Y1Y0 + XY2!Y1!Y0 + XY1Y0 + !X!Y2Y1!Y0 D1 = !X!Y2Y1!Y0 + !XY2Y0 + X!Y2!Y1Y0 + X!Y2Y1!Y0 D0 = X!Y2!Y1Y0 + XY2Y0 + XY1!Y0 + X!Y2!Y0 Y2 Y0

00 01 11 10 1

Y1

1 1 1 1

• 1

Z = Y0 + Y1

The circuit does’t fully respect the characteristics of a real one- shot since the output pulse doesn’t start immediately upon a an input positive edge but only when the clock samples the input 1 X 000 000 101 010 001 000 100 011 110 011 010 1 1 1 001 000 100 110 001 101 000 001 110 1 1 100

(Y2Y1Y0)n (Y2Y1Y0)n+1

47

Mealy solution

48

0,0 0,0 1,1 0,1 XZ 0,0 1,1 0,1 0,1 1,1

G F

1,1

A

1,1

D C B

1

E

1 X A,0 A F,1 C,1 B A,0 E,0 D G,1 D,1 C B,1 A,0 E G,1 B,1 F A,0 B,1 G E,0

Maximal classes A,B,C,(DE),F,G (α,β,χ,δ,φ,γ)

B D C E F

A B C D E F

G

FG CD FG BC DB 1 X 000,0 α 000 100,1 010,1 β 001 000,0 011,0 δ 011 101,1 011,1 χ 010 001,1 101,1 φ 100 000,0 001,1 γ 101 001,1 Y1 Y0

In this case too this is not a perfect one-shot:

49

• The circuit operates ONLY if the input is sampled (as is the case with Moore) which is not always

the case

• The pulse duration is 3 clocks plus the distance between the input activation and the clock
• If during a period (i.e. in γ −> G) there are input variation these impact directly on the output

without waiting for the clock edge!

• Greater is the clock frequency more the circuit approximates the analog one-shot

Counters

A B C D Z

Inputless circuits (but for the clock) in the simplest version

D0 !Q0 Q0 CK DFF M U X 1 D1 !Q1 Q1 CK DFF

(The clock is almost always omitted in the synchronous networks drawings (it is implicit) U0 U1 Carry Q1 switches when Q0 is 1 (and at the first positive clock edge Q0 switches to 0) 50

Example: binary counter x 4 with decoding of 3 (zero…!)

00,0 01,0 10,0 11,1

CK Qu1 Q0 Carry (0) (1) (2) (0) (1) (2) (3) (3) Binary counter x 4 with decoding of 3

51

Non 2’s power counters

D0 !Q0 Q0 CK DFF M U X 1

1

D1 !Q1 Q1 CK DFF M U X 1 D !Q2 Q2 CK DFF

000 001 010 011 100

Base 5 binary counter N.B. Q2Q1Q0

52 A B C D E

This counter counts by 8: but in order to count base 5, after 4 (0,1,2,3,4) the counter must be reset

D0 !Q0 Q0 CK DFF D1 !Q1 Q1 CK DFF M U X 1 D2 !Q2 Q2 CK DFF M U X 1

A B C “4”

Counter x 5

Decoder

When the decoder reaches 4 its output becomes zero and therefore all DFF inputs become 0 and upon the first clock positive edge all FFs outpus become 0

Synthesize a counter x 100 starting from a set of decimal counters (that is a counter base 1010 to be synthesized ). How many FF for a decimal counter ?

“3”

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Counters with control inputs

i.e. An integrated counter base 6 with Load and Enable

• The counter counts base 16 (0-15!!) if EN = 1. When LD is asserted the input data are inserted in the 4 DFFs

(either synchronously or asynchronously). In the previous case the decoder output «4» (positive true) must be connected to LD with all Di zero if LD is synchronous otherwise it is the «5» decoder output which must be connected to LD («5» is therefore an unstable transient state – race problem see later) EN Q0 Q1 Q2 Q3 CK LD D0 D1 D2 D3 EN Q0 Q1 Q2 Q3 CK CY LD D0 D1 D2 D3

• There are UP/DOWN counters whose (U/!D) input selects if the counting is up or down. In case of down

count the carry is generated when all counters FFs are zero.

101 010 000 111 110

Non binary counter x 5

Q2 Q1 Q0

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• In general a 1610 counter generates a “carry” output which is asserted when the counter reaches the value

FH (that is 1510). This output can be connected to the enable of a cascaded counter so as to implement a 25610 counter (00 to FF – never forget the zero!) and so on.

• There is a wealth of different counters, each one with its specific behaviour, with or without RESET (normally

asynchronous) , U/!D, with or without LD etc. etc.

NB: Each synchronous circuit (with non binary sequence too) whose state diagram can be assimilated to that of a counter IS in any case a counter

74163: a 1610 counter with Load, Reset and two anded enables (T and P). The control signals are synchronous that is they act on the clock rising edge 74138: decoder 3:8 with negative true outputs if G2A and G2B zero and G1=1. Otherwise all

• utputs are 1 no matter what is the input

Binary counter x 8 with decoding

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Post-route simulation Disalignment

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000 001 010 011 100 110 111

Q2Q1Q0

101

What happens for the previous base 5 counter upon the power-on if no RESET is available? Unpredictable state which could not belong to the expected cycle. NB The power-on state is absolutely random and depends on the electrical conditions of the circuit Let’ suppose the FFs state is 110 (610, out of the cycle). Let’s analyse the behaviour

In this case after a transient behaviour the system re-enters the regular wanted cycle but the behaviour depends on the implementation and with different implementations the three «external states» could be totally separated from the main cycle which would never be reached. RESET signal !!! 57 D0 !Q0 Q0 CK DFF D1 !Q1 Q1 CK DFF M U X 1 D2 !Q2 Q2 CK DFF M U X 1

A B C “4”

As a didactical example only (never to be used !!!!!!) let’s see the transition table of an Up/!Down base 610 counter (0-5 values) with Reset. The input signals are synchronous To compensate the power-on effect

Sinthesize and simulate

00 01 11 10 Up/!Down Res 000 000 000 000 000 001 010 000 011 001 000 000 011 010 000 001 010 000 100 011 000 100 100 000 000 101 ? ? 111 ? ? ? ? 110 000 101 000 ? ? 101 y3 y2 y1 00 01 11 10 Up/!Down Res 000 000 000 000 000 001 010 000 011 001 000 000 011 010 000 001 010 000 100 011 000 100 100 000 000 101 000 000 111 000 000 000 000 110 000 101 000 000 000 101 y3 y2 y1

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UP/DOWN counter with Reset «Direct» y2 synthesis Let’s find the states where y2 must assume the value «1» 00 01 11 10 Up/!Down Res 000 000 000 000 000 1 001 010 000 3 011 001 000 000 011 2 010 000 001 010 000 100 011 000 4 100 100 000 000 101 000 000 111 000 000 000 000 110 000 101 000 000 000 101 y3 y2 y1

UP/!Down D0 Q0 CK FFD

Clock

y2

D

e c

• d

e r

y3 y2 y1

“1” “2” “3” “4” 1 1

MUX

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Down Up

Safe again …

Using a counter base 8 (but also base 16 etc.) with synchronous reset always enabled how can we implement the opening mechanism of the safe (sequence X1X2 00-01-01-10) Moore model ?

Cx8

RES Q0 Q1 Q2 CK

A B C “0” “1” “2” “3” “4”

RL AND-OR

X1 X2

!RES Z

Cx8

RES Q0 Q1 Q2 CK 60

00 01 01 10 RES= !(“0”!X1!X2 + “1” !X1X2 + “2” !X1X2 + “3” X1 !X2) - counts «+1» if Reset is not active (it is disabled only if for each counter configuration the right input configuration is inserted) (in any case after the opening the counter is reset ) Z = “4” (“0”,”1”,”2”,”3”,”4” are the three outputs binary decoding) The counter is reset whenever the right input (for the particular state) is not fed into the network The counter therefore is reset and keeps reset but for the conditions indicated by the function RES After reaching 4 (Z=1) the counter is reset upon the following clock positive edge The synchronous logical networks are always designed as combinations of standard available blocks and random logic (and, or etc.)

Counters

• Warning !!! Let’s consider the following counter (with asynchronous RESET ) and suppose we

want to count base 5 (N.B. for the Reset we must use in this case «5” …. glitch..)

EN Q0 Q1 Q2 Q3 CK CY RESET

A B C D “5”

“1” Why is this schematic wrong?

• But there is a possible critical race !! When a single DFF is reset (and not necessarily at the same

instant) the decoder doesn’t decode “5” any more and therefore to some FFs the reset is

• cancelled. Then ?

EN Q0 Q1 Q2 Q3 CK CY RESET

A B C D “5”

“1”

R S !Q

“0”

• By so doing “5” activates the SET and the SR FF is not reset until the counter reaches “0”. NB

the «wrong» schematic can be used only if the designer is sure of the reset speed of all counter FFS

• Verify with Xilinx

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Safe synthesis with modules

62 Decoder

RESET control network

Synchronous RESET counter Decoder

Output

Initially the counter is reset with input 01, 10 o 11 (all AND outputs are 0 and therefore the NOR is 1 and the Reset is 1). With input 00 the first AND becomes 1, the reset becomes 0 and the counter counts to 1. If then the input is 01 the second AND becomes 1 and the reset is kept 0. Any

• ther

inputs reactivates the

• RESET. This behaviour is repeated

until the counter reaches 3: the

• utput becomes then 1 and at the

next clock the counter is in any case reset waiting for a successive 00 input.

Post-Route simulation

As forecasted there are delays between inputs and outputs of each device: the total delay is 10 ns . The initial signals high impedace indicates that the network needs an input for the initial stabilisation before a correct behaviour

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