ta8 Spring 200 6 Amar Lior Adapted from Computer - - PowerPoint PPT Presentation

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הנבמ םיבשחמ

ta8

Spring 2006 Amar Lior

Adapted from Computer Organization&Design, H/S interface, Patterson Hennessy@UCB,3rd edition

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Exceptions and Interrupts

Exception: An unscheduled event that

disrupts program execution and change its flow

Interrupts: An exception that comes from

• utside of the processor

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Exception types:

Program

e.g. overflow, division by zero, using undefined

instruction

Invoking the operating system from user

program systemcall

Timer

Generated by internal processor timer Used in pre-emptive multi-tasking

I/O

from I/O controller (keyboard, disk)

Hardware failure

e.g. memory parity error

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System call example

.include "defines.h" .data hello: .string "hello world\n" .text .globl _start _start: movl $SYS_write,%eax // SYS_write = 4 movl $STDOUT,%ebx // fd = fileno(stdio) movl $hello,%ecx // buf = str movl $12,%edx // count = 0x6 int $0x80 movl $SYS_exit,%eax xorl %ebx,%ebx int $0x80 ret

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Program Flow Control

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How Exception are Handled

The address of the affected address is saved

in the EPC register

The cause of the register is used to record

the exception type.

Than the process jump to the exception

address which is the operating system entry point for exception handling

In MIPS 0x8000 0180 In SPIM 0x8000 0080

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Interrupt Cycle

Added to instruction cycle Processor checks for interrupt

Indicated by an interrupt signal

If no interrupt, fetch next instruction If interrupt pending:

Suspend execution of current program Save context Set PC to start address of interrupt handler routine Process interrupt Restore context and continue interrupted program

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Instruction Cycle (with Interrupts) - State Diagram

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Multiple Interrupts

Disable interrupts

Processor will ignore further interrupts whilst processing

• ne interrupt

Interrupts remain pending and are checked after first

interrupt has been processed

Interrupts handled in sequence as they occur

Define priorities

Low priority interrupts can be interrupted by higher

priority interrupts

When higher priority interrupt has been processed,

processor returns to previous interrupt

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Multiple Interrupts - Sequential

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Multiple Interrupts - Nested

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Example - PC Bus

80x86 has one interrupt line 8086 based systems use one 8259A

interrupt controller

8259A has 8 interrupt lines Called Programmable Interrupt Controller

PIC in short.

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Sequence of Events

8259A accepts interrupts 8259A determines priority 8259A signals 8086 (raises INTR line) CPU Acknowledges 8259A puts correct vector on data bus CPU processes interrupt

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PC Interrupt Layout

8086 INTR 8259A IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7

System Timer Keyboard Slave 8259A Serial port Serial port IDE controller Floppy controller LPT1

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The 8086 Interrupt table

Trap

Invalid opcode

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Available for software and hardware interrupts

32-255 Fault

Page Fault

14 Trap

Overflow

4 Trap

Breakpoint

3 Trap Non-Maskable Interrupt (NMI) 2 Trap or Fault Debug exception 1 Fault Divide by zero Type Description Number

• Fault – The return address point to the instruction that

caused the exception

• Trap – The return address points to the instruction after the
• ne that caused the interrupt

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Exception Handling in MIPS (SPIM)

In MIPS processors, a part of the CPU called

coprocessor 0 records the information that software needs to handle exception

Not all the coprocessor 0’s registers are

implemented by SPIM

The mfc0 and mtc0 instructions are used to

access those registers

The EPC contain the address of the offending

instruction (if the exception was internal)

And the address if the next instruction if the

exception was external

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Interrupt related registers

Address of instruction that caused exception 14 Epc Exception type and pending interrupt bits 13 Cause Interrupt mask and enable bits 12 Status Value compared against timer that caused interrupt when they match 11 Compare Timer 9 Count Memory address at which offending memory reference

• ccurred

8 BadVAddr Usage Register Number Register Name

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The Status Register

• The interrupt mask contain a bit for each of the six hardware and two software

interrupt level

• Value of 1 means interrupt from that level can interrupt the processor
• When an interrupt arrive it sets its “interrupt pending” bit in the cause register even if

the mask is 0

• When an interrupt is pending it will interrupt the processor when the mask is enabled.
• The user mode is 0 when in kernel mode and 1 when in user mode (always 1 in

spim)

• The exception level is usually 0 but is set to 1 when exception occur, in this

situation interrupts are disabled and the EPC is not updated if another exception

• ccur. Enable exception handler from being disturbed by an Exception or

interrupt

• If the interrupt enable bit is 1 interrupt are allowed

I n t e r r u p t e n a b l e 1 E x c e p t i

• n

L e v e l 4 U s e r M

• d

e 8 15

Interrupt mask

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Cause Register

The delayed branch is 1 if the last exception

• ccurred in the delay slot of a branch

The interrupt pending bits become 1 when

an interrupt is raised at a given hardware or software level

The exception code describe the cause of the

exception through the codes in next slide

2 6 8 15

Pending Interrupts Exception Code Branch Delay

31

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Exception codes

Floating point exception FPE 15 Trap Tr 13 Arithmetic overflow exception Ov 12 Coprocessor unimplemented CpU 11 Reserved instruction exception RI 10 Breakpoint exception Bp 9 Syscall exception Sys 8 Buss error on data load or store DBE 7 Buss error in instruction fetch IBE 6 Address error exception (store) AdES 5 Address error exception (load or fetch) AdEL 4 Interrupt (hardware) Int

Cause of Exception Name Number

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Handling the Exception

Exception and interrupts cause the MIPS

processor to jump to a piece of code at address 0x8000 0180 (kernel address space)

Called the exception handler This code examine the exception’s code and

jumps to an appropriate point in the

• perating system

The operating system respond by

terminating the process or by performing some action

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Exception handler example