The Belle II Pixel Detector DAQ unchow 1 David M Thomas Geler 1 , - - PowerPoint PPT Presentation

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The Belle II Pixel Detector DAQ unchow 1 David M Thomas Geler 1 , - - PowerPoint PPT Presentation

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The Belle II Pixel Detector DAQ unchow 1 David M Thomas Geler 1 , Igor Konorov 3 , Wolfgang K uhn 1 , S oren Lange 1 , Dmytro Levit 3 , ZhenAn Liu 2 , orn Spruck 1 , Klemens Lautenbach 1 , Jingzhou Zhao 2 Bj 1 University Gieen,

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SLIDE 1

The Belle II Pixel Detector DAQ

David M¨ unchow1

Thomas Geßler1, Igor Konorov3, Wolfgang K¨ uhn1, S¨

  • ren Lange1, Dmytro Levit3, Zhen’An Liu2,

Bj¨

  • rn Spruck1, Klemens Lautenbach1, Jingzhou Zhao2

1University Gießen, Germany; 2IHEP Beijing, China; 3TU Munich, Germany

for the Belle II Collaboration

Instrumentation for Colliding Beam Physics (INSTR14)

  • 24. February - 1. March 2014, BINP

, Novosibirsk, Russia

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SLIDE 2

Overview

1

Belle II at SuperKEKB

2

Vertex detectors

3

Motivation for Data Reduction

4

Belle II VXD DAQ

5

Online Selection Nodes (ONSEN)

6

Test beam setup at DESY

7

First results from test beam

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SLIDE 3

Belle II Experiment at SuperKEKB

Aerial view of KEK and SuperKEKB Belle II experiment

Upgrade of the Belle experiment at KEK in Tsukuba, Japan Asymmetric beam energies of 4 GeV (e+) and 7 GeV (e−), √s = 10.58 GeV Peak luminosity L = 8 · 1035 cm−2 s−1 (40 times previous experiment) Average trigger rate of 30 kHz

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SLIDE 4

Belle II Vertex Detectors (VXD)

Picture by HEPHY, Vienna David M¨ unchow (JLU Gießen) The Belle II Pixel Detector DAQ

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SLIDE 5

Pixel Detector (PXD)

Innermost detector (r = 14 − 22 mm) around beam pipe (r = 12.5 mm outer radius) DEPFET (DEPleted Field Effect Transistor) technology Pixel size 50 × 55 − 60 µm2 (inner layer) and 50 × 70 − 85 µm2 (outer layer) Thickness only 75 µm 40 half ladder in two layers with 768 × 250 pixels per half ladder; in total ∼8 million pixel

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SLIDE 6

Silicon Vertex Detector (SVD)

Picture by HEPHY, Vienna

Second inner detector Double sided silicon strip detector 4 layers; outer 3 layers tilted at forward end Radius: r = 38 − 140 mm

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SLIDE 7

Concept for Region of Interests (ROI)

Row 100 200 300 400 500 600 700 Column 50 100 150 200 250 ADC (electrons) 20 40 60 80 100 3 10 ×

Single Halfladder (inner)

Row 100 200 300 400 500 600 700 Column 50 100 150 200 250 ADC (electrons) 20 40 60 80 100 120 3 10 ×

Single Halfladder (outer)

Inner and outer layer MC background data with Touschek effect

Expected maximum occupancy of 3% dominated by background

(synchrotron radiation, scattering of the beam on residual gas, Touschek scattering, radiative Bhabha scattering (e+e− → e+e−γ), electron-positron pair production (e+e− → e+e−e+e−))

Total data rate >20 GB/s after zero suppression Data reduction needed for event builder and data storage

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SLIDE 8

Concept for Region of Interests (ROI)

Inner layer Touschek background data with one example hit and ROI

Idea: Calculating regions of interest (ROI) by extrapolating particle tracks from outer detectors Two independent tracking systems with different algorithms

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SLIDE 9

Sources for ROIs

Illustrations by Michael Schnell (University of Bonn)

High Level Trigger (HLT) Uses SVD and outer detector data Based on cellular automaton on PC farm Event rejection with software trigger Calculation time up to 5 s Data Concentrator (DatCon) Uses SVD data only Fast Hough transformation FPGA based hardware Calculation time up to 10 µs Both systems extrapolate tracks to PXD layer and send ROIs to ONSEN

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SLIDE 10

Belle II VXD DAQ

PXD Readout PXD Other Detectors PXD SVD SVD Readout Event Builder 1 High Level Trigger Event Builder 2 Concentrator Tracking Merger Storage SVD SVD

ROIs 32 × PXD data Reduced PXD data

PXD PXD

...

40 × PXD 49 × SVD

...

32 × ROI Selector DatCon ONSEN

ROI Selector

ROIs

Diagram of the Belle II VXD DAQ for setup at KEK David M¨ unchow (JLU Gießen) The Belle II Pixel Detector DAQ

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SLIDE 11

Compute Node (CN) rev. 3

AMC daughter board of CN rev. 3 Carrier board with 4 AMC daughter boards

Main hardware for ONSEN and DatCon Developed in cooperation between IHEP Beijing and University Gießen AMC daughter board of CN rev. 3 Xilinx Virtex-5 FX70T Equipped with:

2 × 2 GB RAM 4 × 6.25 Gb/s optical links GBit Ethernet

An additional ATCA based carrier board with following features is under development:

Carries four AMC cards Supplies direct highspeed interconnection between all four AMC Connects all AMC cards to the full mesh ATCA backplane

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SLIDE 12

PXD - Readout

DHH at the test setup at DESY

DHH

4 × ONSEN 5 × PXD

DHH DHH DHH DHH DHHC

Diagram of PXD-Readout with DHH and DHHC

Data Hybrid Handler (DHH):

Slow control of FE-ASICs and DHH via IPBUS Clock and trigger distribution Readout out of PXD Zero suppression Clustering with pipelined neural network cluster processing algorithm Data output via high speed optical link

Data Hybrid Handler Controller (DHHC):

Slow control interface using IPBUS hub Receiving data from 5 DHH Mixed inner and outer layer Load balancing All data of one event combined together Data output to 4 ONSEN

Implemented on FPGA based hardware

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SLIDE 13

ONSEN - ROI Merger Node

HLT-ROI Receiver DatCon-ROI Receiver Merger Logic Merged ROI Sender LUT Buffer Management Multi- Port- Memory

Receive ROIs from DatCon via high speed serial link DatCon ROIs arrive after up to 10 µs and are stored in memory Receive ROIs unordered from HLT via GBit Ethernet (up to 5 s later) As soon as HLT ROIs arrive, corresponding DatCon ROIs of same event are read back from memory HLT and DatCon ROIs are merged Merged ROIs sent to Selection Node Implemented on a CN V.3

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SLIDE 14

ONSEN - ROI Selector Node

PXD Data Receiver HLT/ROI Receiver ROI Selection Selected Data Sender LUT Buffer Management Multi- Port- Memory

Receive pixel data from PXD readout system via high speed serial link Pixel data arrive first and are stored in memory Receive unordered ROIs from Merger Node with delay (up to 5 s) Corresponding pixels of same event are read back from memory Pixel data reduction by ROI selection: Discard pixel if not inside at least one ROI Untriggered data will be rejected Reduced data are sent out to event builder

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SLIDE 15

ROI Selection Core

FiFo data buffer buffer controller ROI buffer format decoder ROI check ROI check 1 ROI check 2 ROI check 3 ROI check n data in (ROI) data in (Pixel) data out (Pixel in ROI)

ROI data Pixel data control signal

Binary pixel data are decoded for further ROI selection. ROI selection is processed for all ROIs of one half ladder in parallel Implemented in FPGA logic

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SLIDE 16

DESY Test Beam Setup

C

  • l

l i m a t

  • r

Fiber γ

e−

Spill Counter M a g n e t Converter

e − e + e+

DESY II

e+/e−

Bremsstrahlung γ beam from synchrotron DESY II Metal plate converter Momentum and rate selection with dipole magnet and collimator

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SLIDE 17

Detector Setup for Test Beam at DESY

Illustration of the simplified detector setup for the test beam at DESY front: beam telescope; behind: SVD

Simplified setup for first test with full DAQ chain

PXD: one sensor SVD: four sensors

Additional beam telescope detectors (pixel detectors) provided by DESY for triggering and correllation studies

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SLIDE 18

Pocket-ONSEN System

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SLIDE 19

Belle II VXD DAQ System at DESY

SVD

Storage Storage Storage

PXD Readout SVD SVD Readout Event Builder 1 High Level Trigger Event Builder 2 Concentrator Tracking Merger ROI Selector Storage SVD SVD

ROIs PXD data Reduced PXD data

PXD

1 × PXD 4 × SVD 1 × ROI Selector DatCon ONSEN

Formatter

ROIs

Diagram of the Belle II VXD DAQ at the test setup at DESY in January 2014 David M¨ unchow (JLU Gießen) The Belle II Pixel Detector DAQ

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SLIDE 20

Results from Test Beam

  • Hitmap before ROI selection

Full DAQ chain established More than 20 million events processed with full chain Full data stream recording for some runs to verify ROI selection

4 GeV beam 1.2 · 106 events Active area on PXD 480 × 128 pixel 4.8 · 108 hits

Picture shows one example run with

186 000 events excluding full matrix ROIs Average occupancy before reduction ∼ 0.80%

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SLIDE 21

Data after ROI Selection

  • Hitmap after ROI selection

Reduced data by ROI selection Real ROIs calculated by tracking algorithms on HLT and DatCon Additional full matrix ROIs for checking Picture shows same example run with

186 000 events excluding full matrix ROIs Average reduced occupancy ∼ 0.12% Average reduction rate ∼ 6.9

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SLIDE 22

Verification of ROI Selection

  • Run with test pattern in ROIs

to illustrate ROI selection

Stable runs checked with full data recording mode Total 1.2 · 106 events with 4.8 · 108 hits PXD hit PXD hit inside ROI

  • utside ROI

Hit in all selected not observed

  • utput data
  • Hit not in

not observed all rejected

  • utput data
  • NO ROI selection errors observed in 1.2 · 106 events

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SLIDE 23

Summary

For the Belle II inner pixel detector a total data rate of >20 GB/s after zero suppression expected Data reduction with a region of interest selection Regions calculated by two separate systems using different tracking algorithms Region of interest selection in hardware on FPGA based Compute Nodes Selection algorithm parallelized in number of ROIs First beam test of combined VXD and full DAQ at DESY

More than 20 million events processed with full chain 1.2 million events with 480 million hits processed with full recording mode to check ROI selection No ROI selection errors observed in 1.2 million events

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SLIDE 24

Thank you for your attention!

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